38-640MHz Low Phase Noise XO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/14/07 Page 1
FEATURES
Less than 0.4ps RMS (12kHz - 20MHz) phase jitter
for all frequencies.
Less than 25ps peak to peak period jitter for all
frequencies.
Low phase noise output (@ 1MHz offset)
o -144dBc/Hz for 106.25MHz
o -144dBc/Hz for 156.25MHz
o -144dBc/Hz for 212.5MHz
o -140dBc/Hz for 312.5MHz,
o -131dBc/Hz for 622.08MHz
Fundamental Crystal Input Frequency:
o 19MHz to 40MHz (3.3V)
o 19MHz to 28.125MHz (2.5V)
Output Frequency:
o 38MHz to 640MHz (3.3V)
o 38MHz to 450MHz (2.5V)
Available in LVPECL, LVDS, or LVCMOS outputs.
Output Enable selector.
2.5V ~ 3.3V operation.
Available in 3x3 QFN or 16-pin TSSOP packages.
DESCRIPTION
The PL680-3X is a monolithic low jitter and low phase
noise high performance clock, capable of producing
0.4ps RMS phase jitter and LVCMOS, LVDS or LVPECL
outputs, covering a wide frequency output range up to
640MHz. It allows high performance and high frequency
output, using a low cost fundamental crystal of 19MHz to
40MHz.
The frequency selector pads of PL680-3X enable output
frequencies of (2, 4, 8, or 16) * F
XIN
. The PL680-3X is
designed to address the demanding requirements of high
performance applications such Fiber Channel, serial ATA,
Ethernet, SAN, etc.
PACKAGE PIN ASSIGNMENT
16-pin TSSOP
3x3 QFN
Note1: QBAR is used for single ended CMOS output.
Note2: ^ Denotes 60kΩ internal pull up resistor.
BLOCK DIAGRAM
1
2
3
4
5
6
7
8
VDDANA
9
10
11
12
13
14
15
16
XIN
XOUT
SEL2^
_CTRL
DNC
GNDANA
LP
SEL0^
GNDBUF
SEL1^
GNDBUF
QBAR
VDDBUF
Q
LM
PL680-3X
GNDBUF
VDDBUF
Q
QBAR
XIN
SEL0^
SEL1^
VDDANA
SEL2^
XOUT
OE_CTRL
DNC
LP
GNDANA
LM
GNDBUF
4
16
15
14
13
12 11 10 9
8
7
6
5
1 2 3
Phase
Detector
Charge Pump
+
Loop Filter
VCO
(F
XiN
x16)
Xtal
Osc
QBAR
OE
XIN
XOUT
VCO
Divider
Q
Performance Tuner
Output
Divider
(1,2,4,8)
SEL[0:2]
