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709369L12PF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
©2018 Integrated Device Technology, Inc.
FEBRUARY 2018
DSC-4845/8
1
Functional Block Diagram
Features
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
◆
High-speed clock to data access
– Commercial: 7.5/9/12ns (max.)
– Insustrial: 9ns (max.)
◆
Low-power operation
– IDT709379/69L
Active: 1.2W (typ.)
Standby: 2.5mW (typ.)
◆
Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
◆
Counter enable and reset features
◆
Dual chip enables allow for depth expansion without
additional logic
◆
Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
◆
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
◆
TTL- compatible, single 5V (±10%) power supply
◆
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
◆
Available in a 100-pin Thin Quad Flatpack (TQFP) package
◆
Green parts available, see ordering information
HIGH-SPEED 32/16K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT709379/69L
0a 1a
0b 1b
0/1
ab
I/O
Control
1
0/1
0
FT
/PIPE
R
R/
W
R
UB
R
LB
R
CE
0R
OE
R
CE
1R
MEMORY
ARRAY
Counter/
Address
Reg.
4845 drw 01
A
14R
(1)
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
I/O
9L
-I/O
17L
I/O
0L
-I/O
8L
I/O
9R
-I/O
17R
I/O
0R
-I/O
8R
A
0L
CLK
L
ADS
L
A
14L
(1)
CNTEN
L
CNTRS T
L
Counter/
Address
Reg.
R/
W
L
UB
L
LB
L
CE
0L
OE
L
CE
1L
1
0/1
0
1b 0b
1a 0a
0/1
ba
I/O
Control
FT
/PIPE
L
NOTE:
1. A
14X is a NC for IDT709369.
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
6.42
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2
INDEX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1009998 979695 949392 9190 8988 8786 8584 838281 8079 7877 76
FT/PIPE
R
OE
R
R/W
R
CN TRST
R
CE
1R
CE
0R
GND
A
12R
A
13R
A
11R
A
10R
A
9R
A
14R
(1)
I
/
O
1
0
R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
GND
UB
R
LB
R
4845 drw 02
I/O
15L
FT/PIPE
L
OE
L
R/W
L
CNTRST
L
CE
1L
CE
0L
V
CC
A
14L
(1)
A
13L
A
12L
A
11L
A
10L
A
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
UB
L
LB
L
GND
I
/
O
5
R
I
/
O
4
R
I
/
O
3
R
I
/
O
2
R
I
/
O
0
R
I
/
O
0
L
G
N
D
I
/
O
2
L
I
/
O
4
L
I
/
O
5
L
I
/
O
6
L
I
/
O
7
L
I
/
O
3
L
I
/
O
1
R
I
/
O
7
R
G
N
D
I
/
O
8
R
I
/
O
9
R
I
/
O
8
L
I
/
O
9
L
I
/
O
6
R
A
7
R
A
8
L
A
7
L
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
A
1
R
A
0
R
C
L
K
R
C
N
T
E
N
R
C
L
K
L
C
N
T
E
N
L
A
0
L
A
2
L
A
3
L
A
5
L
A
6
L
A
1
L
A
4
L
A
8R
G
N
D
V
C
C
I
/
O
1
L
V
C
C
G
N
D
709379/69PF
PN100
(5)
100-Pin TQFP
Top View
(6)
NC
NC
I/O
16R
I/O
17R
I/O
17L
I/O
16L
A
D
S
L
A
D
S
R
.
Pin Configurations
(1,2,3)
NOTES:
1. A14x is a NC for IDT709369.
2. All V
CC pins must be connected to power supply.
3. All GND pins must be connected to ground.
4. Package body is approximately 14mm x 14mm x 1.4mm
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
Description
The IDT709379/69 is a high-speed 32/16K x 18 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
With an input data register, the IDT709379/69 has been optimized for
applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by CE
0 and CE1, permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using CMOS high-performance technology, these
devices typically operate on only 1.2W of power.
6.42
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges
3
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
Truth Table I—Read/Write and Enable Control
(1,2,3)
OE
CLK
CE
0
CE
1
UB LB
R/W
Upper Byte
I/O
9-17
Lower B
yte
I/O
0-8
Mode
X
↑
H X X X X High-Z High-Z Deselected—Power Down
X
↑
X L X X X High-Z High-Z Deselected—Power Down
X
↑
L H H H X High-Z High-Z Both Bytes Deselected
X
↑
LHLHL DATA
IN
High-Z Write to Upper Byte Only
X
↑
LHHLL High-Z DATA
IN
Write to Lower Byte Only
X
↑
LHLLL DATA
IN
DATA
IN
Write to Both Bytes
L
↑
LHLHHDATA
OUT
High-Z Read Upper Byte Only
L
↑
LHHLH High-ZDATA
OUT
Read Lower Byte Only
L
↑
LHLLHDATA
OUT
DATA
OUT
Read Both Bytes
H X L H L L X High-Z High-Z Outputs Disabled
4845 tbl 02
Pin Names
Left Port Right Port Names
CE
0L
,
CE
1L
CE
0R
,
CE
1R
Chip Enables
(3)
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
14L
(1)
A
0R
- A
14R
(1)
Address
I/O
0L
- I/O
17L
I/O
0R
- I/O
17R
Data Input/Output
CLK
L
CLK
R
Clock
UB
L
UB
R
Upper Byte Select
(2)
LB
L
LB
R
Lower Byte Selectt
(2)
ADS
L
ADS
R
Address Strobe
CNTEN
L
CNTEN
R
Counter Enable
CNTRST
L
CNTRST
R
Counter Reset
FT/PIPE
L
FT/PIPE
R
Flow-Through/Pipeline
V
CC Power
GND Ground
4845 tbl 01
NOTES:
1. A14x is a NC for IDT709369.
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CEo and CE
1 are single buffered when FT/PIPE = VIL,
CEo and CE
1 are double buffered when FT/PIPE = VIH,
i.e. the signals take two cycles to deselect.
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709369L12PF8

Mfr. #:
Buy 709369L12PF8
Manufacturer:
IDT
Description:
SRAM 16K X 18K
Lifecycle:
New from this manufacturer.
Delivery:
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