6.42
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges
4
Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to
< 20mA for the period of VTERM > VCC + 10%.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
Absolute Maximum Ratings
(1)
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
3. C
OUT also references CI/O.
Capacitance
(1)
(TA = +25°C, f = 1.0MHz)
NOTES:
1. This is the parameter T
A. This is the "instant on" case temperature.
NOTES:
1. V
TERM must not exceed VCC + 10%.
2. V
IL > -1.5V for pulse width less than 10ns.
Grade Ambient
Temperature
(2)
GND V
CC
Commercial 0
O
C to +70
O
C0V 5.0V
+
10%
Industrial -40
O
C to +85
O
C0V 5.0V
+
10%
4845 tbl 04
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supply Voltage 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Input High Voltage 2.2
____
6.0
(1)
V
V
IL
Input Low Voltage -0.5
(2)
____
0.8 V
4845 tbl 05
Symbol Parameter Conditions
(2)
Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 9 pF
C
OUT
(3 )
Output Capacitance V
OUT
= 3dV 10 pF
4845 tbl 07
Symbol Rating Commercial
& Industrial
Unit
V
TERM
(2)
Terminal Voltage
with Respect
to GND
-0.5 to +7.0 V
T
BIAS
Temperature Under Bias -55 to +125
o
C
T
STG
Storage Temperature -65 to +150
o
C
T
JN
Junction Temperature +150
o
C
I
OUT
DC Output Current 50 mA
4845 tbl 06
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. CE
0, LB, UB, and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS is independent of all other signals including CE
0, CE1, UB and LB.
5. The address counter advances if CNTEN = V
IL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
6. While an external address is being loaded (ADS = V
IL), R/W = VIH is recommended to ensure data is not written arbitrarily.
Truth Table II—Address Counter Control
(1,2,6)
External
Address
Previous
Internal
Address
Internal
Address
Used CLK
ADS CNTEN CNTRST
I/O
(3)
MODE
An X An
↑
L
(4)
XHD
I/O
(n) External Address Used
XAnAn + 1
↑
H L
(5)
HD
I/O
(n+1) Counter Enabled—Internal Address generation
X An + 1 An + 1
↑
HH HD
I/O
(n+1) External Address Blocked—Counter disabled (An + 1 reused)
XXA
0
↑
XX L
(4)
D
I/O
(0) Counter Reset to Address 0
4845 tbl 03
