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72V85L15PAG

P1-P3P4-P6P7-P9P10-P12
1
DSC-3966/5
©
JUNE 2012
IDT72V81
IDT72V82
IDT72V83
IDT72V84
IDT72V85
3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO
DUAL 512 x 9, DUAL 1,024 x 9
DUAL 2,048 x 9, DUAL 4,096 X 9
DUAL 8,192 X 9
2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The AsyncFIFO™ is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEATURES:
••
••
• The IDT72V81 is equivalent to two IDT72V01 - 512 x 9 FIFOs
••
••
• The IDT72V82 is equivalent to two IDT72V02 - 1,024 x 9 FIFOs
••
••
• The IDT72V83 is equivalent to two IDT72V03 - 2,048 x 9 FIFOs
••
••
• The IDT72V84 is equivalent to two IDT72V04 - 4,096 x 9 FIFOs
••
••
• The IDT72V85 is equivalent to two IDT72V05 - 8,192 x 9 FIFOs
••
••
• Low power consumption
— Active: 330 mW (max.)
— Power-down: 18 mW (max.)
••
••
• Ultra high speed—15 ns access time
••
••
• Asynchronous and simultaneous read and write
••
••
• Offers optimal combination of data capacity, small foot print
and functional flexibility
••
••
• Ideal for bidirectional, width expansion, depth expansion, bus-
matching, and data sorting applications
••
••
• Status Flags: Empty, Half-Full, Full
••
••
• Auto-retransmit capability
••
••
• High-performance CMOS™ technology
••
••
• Space-saving TSSOP package
••
••
• Industrial temperature range (–40
°°
°°
°C to +85
°°
°°
°C) is available
••
••
• Green parts available, see ordering information
DESCRIPTION:
The IDT72V81/72V82/72V83/72V84/72V85 are dual-FIFO memories that
load and empty data on a first-in/first-out basis. These devices are functional and
compatible to two IDT72V01/72V02/72V03/72V04/72V05 FIFOs in a single
package with all associated control, data, and flag lines assigned to separate
pins. The devices use Full and Empty flags to prevent data overflow and
underflow and expansion logic to allow for unlimited expansion capability in both
word size and depth.
The reads and writes are internally sequential through the use of ring
pointers, with no address information required to load and unload data. Data
is toggled in and out of the devices through the use of the Write (W) and Read
(R) pins.
The devices utilize a 9-bit wide data array to allow for control and parity
bits at the user’s option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability that allows for reset
of the read pointer to its initial position when RT is pulsed low to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
These FIFOs are fabricated using high-speed CMOS technology. They are
designed for those applications requiring asynchronous and simultaneous
read/writes in multiprocessing and rate buffer applications.
FUNCTIONAL BLOCK DIAGRAM
WA
WRITE
CONTROL
READ
CONTROL
RA
FLAG
LOGIC
EXPANSION
LOGIC
XIA
WRITE
POINTER
RAM
ARRAY A
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
READ
POINTER
DATA INPUTS
RESET
LOGIC
THREE-
STATE
BUFFERS
DATA
OUTPUTS
RSA
FLA/RTA
XOA/HFA
FFA EFA
WB
WRITE
CONTROL
READ
CONTROL
RB
FLAG
LOGIC
EXPANSION
LOGIC
XIB
WRITE
POINTER
READ
POINTER
DATA INPUTS
RESET
LOGIC
THREE-
STATE
BUFFERS
DATA
OUTPUTS
RSB
FLB/RTB
3966 drw 01
XOB/HFB
FFB EFB
(DA
0
-DA
8
)
(QA
0
-QA
8
)
(QB
0
-QB
8
)
(DB
0
-DB
8
)
RAM
ARRAY A
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
PIN CONFIGURATION
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 3.0 3.3 3.6 V
GND Supply Voltage 0 0 0 V
V
IH
(1)
Input High Voltage 2.0 — VCC+0.5 V
VIL
(2)
Input Low Voltage — — 0.8 V
TA Operating Temperature Commercial 0 — 70 °C
T
A Operating Temperature Industrial -40 — 85 °C
RECOMMENDED DC OPERATING
CONDITIONS
FFA
QA
0
QA
1
QA
2
QA
3
QA
8
GND
RA
QA
4
QA
5
QA
6
QA
7
XOA/HFA
EFA
FFB
QB
0
QB
1
QB
2
QB
3
QB
8
GND
RB
QB
4
QB
5
QB
6
QB
7
XOB/HFB
EFB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
XIA
DA
0
DA
1
DA
2
DA
3
DA
8
WA
V
CC
DA
4
DA
5
DA
6
DA
7
FLA/RTA
RSA
XIB
DB
0
DB
1
DB
2
DB
3
DB
8
WB
V
CC
DB
4
DB
5
DB
6
DB
7
FLB/RTB
RSB
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
3966 drw 02
TSSOP (SO56-2, order code: PA)
TOP VIEW
NOTES:
1. For RT/RS/XI input, VIH = 2.6V (commercial and industrial).
2. 1.5V undershoots are allowed for 10ns once per cycle
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1
3966 drw 03
30pF*
330Ω
3.3V
TO
OUTPUT
PIN
510Ω
or equivalent circuit
Figure 1. Output Load
*Includes scope and jib capacitances.
CAPACITANCE (TA = +25°C, f = 1.0 MHz)
Symbol Parameter
(1)
Condition Max. Unit
C
IN Input Capacitance VIN = 0V 8 pF
COUT Output Capacitance VOUT = 0V 8 pF
NOTE:
1. Characterized values, not currently tested.
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs open (IOUT = 0).
4. Tested at f = 20 MHz.
5. All Inputs = VCC - 0.2V or GND + 0.2V.
DC ELECTRICAL CHARACTERISTICS
(1)
(Commercial: VCC = 3.3V±0.3V, TA = 0°C to +70°C;
Industrial: VCC = 3.3V±0.3V, TA = -40°C to +85°C)
Commercial Industrial
tA = 15, 20 ns tA = 20 ns
Symbol Parameter Min. Max. Min. Max. Unit
I
LI
(1)
Input Leakage Current (Any Input) –1 1 –1 1 μA
ILO
(2)
Output Leakage Current –10 10 –10 10 μA
VOH Output Logic “1” Voltage IOH = –2mA 2.4 — 2.4 — V
V
OL Output Logic “0” Voltage IOL = 8mA — 0.4 — 0.4 V
ICC1
(3,4)
Active Power Supply Current (both FIFOs) — 100 — 120 mA
ICC2
(3,5)
Standby Current (R=W=RS=FL/RT=VIH)—5—5mA
ABSOLUTE MAXIMUM RATINGS
Symbol Rating Com'l & Ind'l Unit
V
TERM Terminal Voltage –0.5 to +7.0 V
with Respect to GND
T
STG Storage Temperature –55 to +125 °C
I
OUT DC Output Current –50 to +50 mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
3
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Commercial Commercial & Industrial
IDT72V81L15 IDT72V81L20
IDT72V82L15 IDT72V82L20
IDT72V83L15 IDT72V83L20
IDT72V84L15 IDT72V84L20
IDT72V85L15 IDT72V85L20
Symbol Parameter Min. Max. Min. Max. Unit
tS Shift Frequency — 40 — 33.3 M H z
tRC Read Cycle Time 25 — 30 — ns
tA Access Time — 15 — 20 ns
tRR Read Recovery Time 10 — 10 — ns
tRPW Read Pulse Width
(2)
15 — 20 — ns
tRLZ Read Pulse Low to Data Bus at Low Z
(3)
3—3—ns
tWLZ Write Pulse High to Data Bus at Low Z
(3, 4)
5—5—ns
t
DV Data Valid from Read Pulse High 5 — 5 — ns
tRHZ Read Pulse High to Data Bus at High Z
(3)
—15—15ns
tWC Write Cycle Time 25 — 30 — ns
tWPW Write Pulse Width
(2)
15 — 20 — ns
tWR Write Recovery Time 10 — 10 — ns
tDS Data Set-up Time 11 — 12 — ns
tDH Data Hold Time 0 — 0 — ns
tRSC Reset Cycle Time 25 — 30 — ns
tRS Reset Pulse Width
(2)
15 — 20 — ns
tRSS Reset Set-up Time
(3)
15 — 20 — ns
t
RSR Reset Recovery Time 10 — 10 — ns
tRTC Retransmit Cycle Time 25 — 30 — ns
tRT Retransmit Pulse Width
(2)
15 — 20 — ns
tRTS Retransmit Set-up Time
(3)
15 — 20 — ns
tRTR Retransmit Recovery Time 10 — 10 — ns
tEFL Reset to Empty Flag Low — 25 — 30 ns
tHFH,FFH Reset to Half-Full and Full Flag High — 25 — 30 ns
tRTF Retransmit Low to Flags Valid — 25 — 30 ns
tREF Read Low to Empty Flag Low — 15 — 20 ns
tRFF Read High to Full Flag High — 15 — 20 ns
tRPE Read Pulse Width after EF High 15 — 20 — ns
tWEF Write High to Empty Flag High — 15 — 20 ns
tWFF Write Low to Full Flag Low — 15 — 20 ns
tWHF Write Low to Half-Full Flag Low — 25 — 30 ns
tRHF Read High to Half-Full Flag High — 25 — 30 ns
tWPF Write Pulse Width after FF High 15 — 20 — ns
tXOL Read/Write to XO Low — 15 — 20 ns
tXOH Read/Write to XO High — 15 — 20 ns
tXI XI Pulse Width
(2)
15 — 20 — ns
tXIR XI Recovery Time 10 — 10 — ns
tXIS XI Set-up Time 10 — 10 — ns
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
AC ELECTRICAL CHARACTERISTICS
(1)
(Commercial: VCC = 3.3V±0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V±0.3V, TA = -40°C to +85°C)
P1-P3P4-P6P7-P9P10-P12

72V85L15PAG

Mfr. #:
Buy 72V85L15PAG
Manufacturer:
IDT
Description:
FIFO 8Kx9 ASYNCHRONOUS DUAL FIFO 3.3V
Lifecycle:
New from this manufacturer.
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