GS1574 Data Sheet
28854 - 5 May 2007 10 of 18
Figure 3-4: MUTE Circuit
Figure 3-5: Bypass Circuit
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MUTE
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CC
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B
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Internal
Referenc
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GS1574 Data Sheet
28854 - 5 May 2007 11 of 18
4. Detailed Description
The GS1574 is a high speed bipolar IC designed to equalize serial digital signals.
The GS1574 can equalize both HD and SD serial digital signals, and will typically
equalize greater than 140m of Belden 1694A cable at 1.
485Gb/
s and 350m at
270Mb/s.
The GS1574 is powered from a single +3.3V power supply and consumes
approximately 270mW of power.
4.1 Serial Digital Inputs
The serial data signal may be connected to the input pins (SDI/SDI) in either a
differential or single ended configuration. AC coupling of the inputs is
recommended, as the SDI and SDI
inputs are internally biased at approximately
1.8V.
4.2 Cable Equalization
The input signal passes through a variable gain equalizing stage whose frequency
response closely matches the inverse of the cable loss characteristic.
The edge energy of the equalized signal is monitored by a detector circuit which
produces an error signal corresponding to the difference between the desired edge
energy and the actual edge energy. This error signal is integrated by both an
internal and an external AGC filter capacitor providing a steady control voltage for
the gain stage. As the frequency response of the gain stage is automatically varied
by the application of negative feedback, the edge energy of the equalized signal is
kept at a constant level which is representative of the original edge energy at the
transmitter. The equalized signal is also DC restored, effectively restoring the logic
threshold of the equalized signal to its correct level independent of shifts due to AC
coupling. The digital output signals have a nominal voltage of 750mV
pp
differential,
or 375mV
pp
single ended when terminated with 50 as shown in Figure 4-1.
GS1574 Data Sheet
28854 - 5 May 2007 12 of 18
Figure 4-1: Typical Output Voltage Levels
4.3 Programmable Mute Output
For SMPTE 259M inputs, the GS1574 incorporates a programmable threshold
output mute (MCLADJ).
In applications where there are multiple input channels using the GS1574, it is
advantageous to have a programmable mute output to avoid signal crosstalk.
The output of the GS1574 can be muted when the input signal decreases below a
certain input level. This threshold is determined using the input voltage applied to
the MCLADJ pin. The MCLADJ pin may be left unconnected for applications where
output muting is not required.
This feature has been designed for use in applications such as routers where
signal crosstalk and circuit noise cause the equalizer to output erroneous data
when no input signal is present. The use of a Carrier Detect function with a fixed
internal reference does not solve this problem since the signal to noise ratio on the
circuit board could be significantly less than the default signal detection level set by
the on chip reference.
NOTE: MCLADJ is only recommended for data rates up to 360Mb/s. For data rates
above this MCLADJ should be left floating.
4.4 Mute
In addition to the programmable mute output, the GS1574 includes a MUTE input
pin that allows the application interface to mute the serial digital output at any time.
Set the MUTE pin HIGH to mute SDO and SDO
.
50 50
SDO
SDO
+187.5mV
-187.5mV
V
CM
= 2.925V
typical
+187.5mV
-187.5mV
V
CM
= 2.925V
typical

GS1574-CTE3

Mfr. #:
Manufacturer:
Semtech
Description:
Equalizers QFN-16 Pin Taped (250/reel)
Lifecycle:
New from this manufacturer.
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