NBA3N201S
www.onsemi.com
7
Table 7. RECEIVER AC CHARACTERISTICS VCC = 3.3 ±10% V( 3.0 to 3.6 V), GND = 0 V, T
A
= −40°C to +125°C (Note 7)
Symbol
Characteristic Min Typ Max Unit
t
PLH
/ t
PHL
Propagation Delay (See Figure 12) 2 4 6 ns
t
PHZ
/ t
PLZ
Disable Time HIGH or LOW state to High Impedance (See Figure 13) 10 ns
t
PZH
/ t
PZL
Enable Time High Impedance to HIGH or LOW state (See Figure 13) 18 ns
t
SK(P)
Pulse Skew (|t
PLH
− t
PHL
|) (See Figure 14) C
L
= 5 pF
Type 1
100 400
ps
t
SK(PP)
Device to Device Skew similar path and conditions (See Figure 12) C
L
= 5 pF 1 ns
t
JIT(PER)
Period Jitter RMS, 100 MHz (Source: VID = 200 mV
pp
V
CM
=1 V, tr/tf 0.5 ns, 10 and 90
% points, 30k samples. Source jitter de−embedded from Output values ) (See Fig-
ure 14)
4 8 ps
t
JIT(PP)
Peak−to−peak Jitter, 200 Mbps 2
15
−1 PRBS (Source tr/tf 0.5 ns, 10% and 90% points,
100k samples. Source jitter de−embedded from Output values) (See Figure 14)
Type 1
300 800
ps
tr / tf Differential Output rise and fall times (See Figure 14) C
L
= 15 pF 1 2.3 ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Typ value at 25°C and 3.3 VCC supply voltage. .
Figure 3. Driver Voltage and Current Definitions
A. All resistors are 1% tolerance.
Figure 4. Differential Output Voltage Test Circuit
NBA3N201S
www.onsemi.com
8
A. All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse frequency = 500 kHz,
duty cycle = 50 ± 5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20% tolerance.
C. R1 and R2 are metal film, surface mount, 1% tolerance, and located within 2 cm of the D.U.T.
D. The measurement of V
OS(PP) is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 5. Test Circuit and Definitions for the Driver Common−Mode Output Voltage
Figure 6. Driver Short−Circuit Test Circuit
A. All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, frequency = 500 kHz,
duty cycle = 50 ±5%.
B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20%.
C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a −3 dB bandwidth of at least 1 GHz.
Figure 7. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
NBA3N201S
www.onsemi.com
9
A. All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, frequency = 500 kHz,
duty cycle = 50 ±5%.
B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20%.
C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a −3 dB bandwidth of at least 1 GHz.
Figure 8. Driver Enable and Disable Time Circuit and Definitions
Figure 9. Maximum Steady State Output Voltage
V
A
or V
B

NBA3N201SDG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer MLVDS DRIVER RECEIVER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet