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AD5333BRUZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
REV. 0
AD5332/AD5333/AD5342/AD5343
–7–
AD5342 FUNCTIONAL BLOCK DIAGRAM
V
OUT
A
BUFFER
AD5342
V
OUT
B
BUFFER
POWER-ON
RESET
DAC
REGISTER
DAC
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INTER-
FACE
LOGIC
V
DD
DB
11
DB
0
CS
WR
A0
CLR
LDAC
.
.
.
V
REF
A
POWER-DOWN
LOGIC
RESET
PD
GND
V
REF
B
12-BIT
DAC
12-BIT
DAC
AD5342 PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0-V
REF
or 0-2 V
REF
.
2 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
3V
REF
B Reference Input for DAC B.
4V
REF
A Reference Input for DAC A.
5V
OUT
A Output of DAC A. Buffered output with rail-to-rail operation.
6V
OUT
B Output of DAC B. Buffered output with rail-to-rail operation.
7, 8 NC No Connect.
9 GND Ground reference point for all circuitry on the part.
10 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
11 WR Active low Write Input. This is used in conjunction with CS to write data to the parallel interface.
12 A0 Address pin for selecting between DAC A and DAC B.
13 CLR Asynchronous active low control input that clears all input registers and DAC registers to zeros.
14 LDAC Active low control input that updates the DAC registers with the contents of the input registers. This
allows all DAC outputs to be simultaneously updated.
15 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
16 V
DD
Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 ␮F capacitor in parallel with a 0.1 ␮F capacitor to GND.
17–28 DB
0
–DB
11
12 Parallel Data Inputs. DB
11
is the MSB of these 12 bits.
AD5342 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD5342
LDAC
A0
WR
CS
GND
BUF
V
REF
B
V
REF
A
V
OUT
B
V
OUT
A
GAIN
PD
V
DD
DB
0
DB
1
DB
2
DB
3
DB
4
DB
9
DB
8
DB
5
DB
6
DB
7
12-BIT
NC
NC
CLR
DB
10
DB
11
NC = NO CONNECT
REV. 0
AD5332/AD5333/AD5342/AD5343
–8–
AD5343 FUNCTIONAL BLOCK DIAGRAM
.
.
.
.
.
.
V
OUT
A
BUFFER
GND
AD5343
V
OUT
B
PD
LOW BYTE
REGISTER
V
DD
V
REF
HBEN
DB
7
DB
0
CS
WR
A0
CLR
LDAC
RESET
POWER-ON
RESET
HIGH BYTE
REGISTER
LOW BYTE
REGISTER
HIGH BYTE
REGISTER
POWER-DOWN
LOGIC
DAC
REGISTER
DAC
REGISTER
INTER-
FACE
LOGIC
BUFFER
12-BIT
DAC
12-BIT
DAC
AD5343 PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1 HBEN This pin is used when writing to the device to determine if data is written to the high byte register or the
low byte register.
2V
REF
Unbuffered reference input for both DACs.
3V
OUT
A Output of DAC A. Buffered output with rail-to-rail operation.
4V
OUT
B Output of DAC B. Buffered output with rail-to-rail operation.
5 GND Ground reference point for all circuitry on the part.
6 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
7 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
8 A0 Address pin for selecting between DAC A and DAC B.
9 CLR Asynchronous active low control input that clears all input registers and DAC registers to zeros.
10 LDAC Active low control input that updates the DAC registers with the contents of the input registers. This allows
all DAC outputs to be simultaneously updated.
11 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
12 V
DD
Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 ␮F capacitor in parallel with a 0.1 ␮F capacitor to GND.
13–20 DB
0
–DB
7
Eight Parallel Data Inputs. DB
7
is the MSB of these eight bits.
AD5343 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD5343
LDAC
A0
WR
CS
GND
V
REF
V
OUT
B
V
OUT
A
PD
V
DD
DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
12-BIT
CLR
HBEN
REV. 0
AD5332/AD5333/AD5342/AD5343
–9–
TERMINOLOGY
RELATIVE ACCURACY
For the DAC, Relative Accuracy or Integral Nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. Typical INL versus Code plot can be seen in Figures
5, 6, and 7.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ± 1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono-
tonic by design. Typical DNL versus Code plot can be seen in
Figures 8, 9, and 10.
OFFSET ERROR
This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.
If the offset voltage is positive, the output voltage will still be
positive at zero input code. This is shown in Figure 3. Because
the DACs operate from a single supply, a negative offset cannot
appear at the output of the buffer amplifier. Instead, there will
be a code close to zero at which the amplifier output saturates
(amplifier footroom). Below this code there will be a deadband
over which the output voltage will not change. This is illustrated
in Figure 4.
GAIN ERROR
This is a measure of the span error of the DAC (including any
error in the gain of the buffer amplifier). It is the deviation in
slope of the actual DAC transfer characteristic from the ideal
expressed as a percentage of the full-scale range. This is illus-
trated in Figure 2.
DAC CODE
POSITIVE
GAIN ERROR
NEGATIVE
GAIN ERROR
OUTPUT
VOLTAGE
ACTUAL
IDEAL
Figure 2. Gain Error
DAC CODE
POSITIVE
OFFSET
OUTPUT
VOLTAGE
GAIN ERROR
AND
OFFSET
ERROR
ACTUAL
IDEAL
Figure 3. Positive Offset Error and Gain Error
OUTPUT
VOLTAGE
DAC CODE
NEGATIVE
OFFSET
GAIN ERROR
AND
OFFSET
ERROR
AMPLIFIER
FOOTROOM
(~ 1mV)
NEGATIVE
OFFSET
DEADBAND CODES
ACTUAL
IDEAL
Figure 4. Negative Offset Error and Gain Error
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

AD5333BRUZ-REEL

Mfr. #:
Buy AD5333BRUZ-REEL
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC IC 10-BIT DUAL
Lifecycle:
New from this manufacturer.
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