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AD5343BRUZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
REV. 0
AD5332/AD5333/AD5342/AD5343
–4–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5332/AD5333/AD5342/AD5343 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to V
DD
+ 0.3 V
Reference Input Voltage to GND . . . . –0.3 V to V
DD
+ 0.3 V
V
OUT
to GND . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
TSSOP Package
Power Dissipation . . . . . . . . . . . . . . . (T
J
max – T
A
)/θ
JA
mW
θ
JA
Thermal Impedance (20-Lead TSSOP) . . . . . 143°C/W
θ
JA
Thermal Impedance (24-Lead TSSOP) . . . . . 128°C/W
θ
JA
Thermal Impedance (28-Lead TSSOP) . . . . 97.9°C/W
θ
JC
Thermal Impedance (20-Lead TSSOP) . . . . . . 45°C/W
θ
JC
Thermal Impedance (24-Lead TSSOP) . . . . . . 42°C/W
θ
JC
Thermal Impedance (28-Lead TSSOP) . . . . . . 14°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Package
Model Temperature Range Package Description Option
AD5332BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-20
AD5333BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-24
AD5342BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-28
AD5343BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-20
REV. 0
AD5332/AD5333/AD5342/AD5343
–5–
AD5332 FUNCTIONAL BLOCK DIAGRAM
POWER-ON
RESET
DAC
REGISTER
DAC
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INTER-
FACE
LOGIC
DB
7
DB
0
CS
WR
A0
CLR
LDAC
.
.
.
V
REF
A
RESET
V
REF
B
V
OUT
A
BUFFER
AD5332
V
OUT
B
BUFFER
V
DD
POWER-DOWN
LOGIC
PD
GND
8-BIT
DAC
8-BIT
DAC
AD5332 PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1V
REF
B Unbuffered reference input for DAC B.
2V
REF
A Unbuffered reference input for DAC A.
3V
OUT
A Output of DAC A. Buffered output with rail-to-rail operation.
4V
OUT
B Output of DAC B. Buffered output with rail-to-rail operation.
5 GND Ground reference point for all circuitry on the part.
6 CS Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
7 WR Active low Write Input. This is used in conjunction with CS to write data to the parallel interface.
8 A0 Address pin for selecting which DAC A and DAC B.
9 CLR Asynchronous active low control input that clears all input registers and DAC registers to zeros.
10 LDAC Active low control input that updates the DAC registers with the contents of the input registers. This
allows all DAC outputs to be simultaneously updated.
11 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
12 V
DD
Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 ␮F capacitor in parallel with a 0.1 ␮F capacitor to GND.
13–20 DB
0
–DB
7
Eight Parallel Data Inputs. DB
7
is the MSB of these eight bits.
AD5332 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD5332
LDAC
A0
WR
CS
GND
V
REF
B
V
REF
A
V
OUT
B
V
OUT
A
PD
V
DD
DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
8-BIT
CLR
REV. 0
AD5332/AD5333/AD5342/AD5343
–6–
AD5333 FUNCTIONAL BLOCK DIAGRAM
POWER-ON
RESET
DAC
REGISTER
DAC
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INTER-
FACE
LOGIC
DB
9
DB
0
CS
WR
A0
CLR
LDAC
.
.
.
V
REF
A
RESET
V
REF
B
BUF
GAIN
10-BIT
DAC
10-BIT
DAC
V
OUT
A
BUFFER
AD5333
V
OUT
BBUFFER
V
DD
POWER-DOWN
LOGIC
PD
GND
AD5333 PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–V
REF
or 0–2 V
REF
.
2 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
3V
REF
B Reference input for DAC B.
4V
REF
A Reference input for DAC A.
5V
OUT
A Output of DAC A. Buffered output with rail-to-rail operation.
6V
OUT
B Output of DAC B. Buffered output with rail-to-rail operation.
7 GND Ground reference point for all circuitry on the part.
8 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
9 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
10 A0 Address pin for selecting between DAC A and DAC B.
11 CLR Asynchronous active-low control input that clears all input registers and DAC registers to zeros.
12 LDAC Active-low control input that updates the DAC registers with the contents of the input registers. This
allows all DAC outputs to be simultaneously updated.
13 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
14 V
DD
Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 ␮F capacitor in parallel with a 0.1 ␮F capacitor to GND.
15–24 DB
0
–DB
9
10 Parallel Data Inputs. DB
9
is the MSB of these 10 bits.
AD5333 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD5333
LDAC
A0
WR
CS
GAIN
V
REF
B
V
OUT
A
GND
PD
V
DD
DB
0
DB
1
DB
2
DB
7
DB
6
DB
3
DB
4
DB
5
10-BIT
V
OUT
B
V
REF
A
BUF
CLR
DB
8
DB
9
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

AD5343BRUZ-REEL

Mfr. #:
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Manufacturer:
Description:
Digital to Analog Converters - DAC 12-BIT DUAL BYTE IC
Lifecycle:
New from this manufacturer.
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