NCV4275A
www.onsemi.com
11
Calculating Power Dissipation
in a Single Output Linear Regulator
The maximum power dissipation for a single output
regulator (Figure 25) is:
D(max)
+ [V
I(max)
* V
Q(min)
]I
Q(max)
(
) V
I(max)
I
q
where
V
I(max)
is the maximum input
voltage,
V
Q(min)
is the minimum output
voltage,
I
Q(max)
is the maximum output
current for the application,
I
q
is the quiescent current the regulator consumes
at I
Q(max)
.
Once the value of P
D(max)
is known, the maximum
permissible value of R
JA
can be calculated:
R
JA
+
150° C *
T
A
P
D
(2)
The value of R
JA
can then be compared with those in the
package section of the data sheet. Those packages with
R
JA
’s less than the calculated value in Equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
SMART
REGULATOR®
Iq
Control
Features
I
Q
I
I
Figure 25. Single Output Regulator with Key
Performance Parameters Labeled
V
I
V
Q
}
Heatsinks
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and
the outside environment will have a thermal resistance.
Like series electrical resistances, these resistances are
summed to determine the value of R
JA
:
R
JA
+ R
JC
) R
CS
) R
SA
(3)
where
R
JC
is the junction−to−case thermal resistance,
R
CS
is the case−to−heatsink thermal resistance,
R
SA
is the heatsink−to−ambient thermal resistance.
R
JC
appears in the package section of the data sheet.
Like R
JA
, it too is a function of package type. R
CS
and
R
SA
are functions of the package type, heatsink and the
interface between them. These values appear in heatsink
data sheets of heatsink manufacturers.
Thermal, mounting, and heatsinking considerations are
discussed in the ON Semiconductor application note
AN1040/D.
Thermal Model
A discussion of thermal modeling is in the ON Semiconductor web site: http://www.onsemi.com/pub/collateral/BR1487−D.PDF.
Table 1. DPAK 5−Lead Thermal RC Network Models
Drain Copper Area (1 oz thick) 168 mm
2
736 mm
2
168 mm
2
736 mm
2
(SPICE Deck Format) Cauer Network Foster Network
168 mm
2
736 mm
2
Units Ta u Ta u Units
C_C1 Junction Gnd 1.00E−06 1.00E−06 W−s/C 1.36E−08 1.361E−08 sec
C_C2 node1 Gnd 1.00E−05 1.00E−05 W−s/C 7.41E−07 7.411E−07 sec
C_C3 node2 Gnd 6.00E−05 6.00E−05 W−s/C 1.04E−05 1.029E−05 sec
C_C4 node3 Gnd 1.00E−04 1.00E−04 W−s/C 3.91E−05 3.737E−05 sec
C_C5 node4 Gnd 4.36E−04 3.64E−04 W−s/C 1.80E−03 1.376E−03 sec
C_C6 node5 Gnd 6.77E−02 1.92E−02 W−s/C 3.77E−01 2.851E−02 sec
C_C7 node6 Gnd 1.51E−01 1.27E−01 W−s/C 3.79E+00 9.475E−01 sec
C_C8 node7 Gnd 4.80E−01 1.018 W−s/C 2.65E+01 1.173E+01 sec
C_C9 node8 Gnd 3.740 2.955 W−s/C 8.71E+01 8.59E+01 sec
