IDT
®
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463E — 07/20/11
9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
11
Datasheet
SMBusTable: Output, and PLL BW Control Register
Pin # Name Control Function T
e0 1PWD
Bit 7
RW Latch
Bit 6
RW Latch
Bit 5
DIF_17 Output Control RW Hi-Z Enable 1
Bit 4
DIF_16 Output Control RW Hi-Z Enable 1
Bit 3
0
Bit 2
100M_133M# Frequenc
Select Bit C R
133MHz 100MHz Latch
Bit 1
FSB Frequency Select Bit B RW 0
Bit 0
FSA Frequency Select bit A RW 1
SMBusTable: Output Control Register
Pin # Name Control Function T
e0 1PWD
Bit 7
DIF_7 Output Control R
Hi-Z Enable 1
Bit 6
DIF_6 Output Control RW Hi-Z Enable 1
Bit 5
DIF_5 Output Control RW Hi-Z Enable 1
Bit 4
DIF_4 Output Control RW Hi-Z Enable 1
Bit 3
DIF_3 Output Control R
Hi-Z Enable 1
Bit 2
DIF_2 Output Control RW Hi-Z Enable 1
Bit 1
DIF_1 Output Control RW Hi-Z Enable 1
Bit 0
DIF_0 Output Control RW Hi-Z Enable 1
SMBusTable: Output Control Register
Pin # Name Control Function T
e0 1PWD
Bit 7
DIF_15 Output Control RW Hi-Z Enable 1
Bit 6
DIF_14 Output Control RW Hi-Z Enable 1
Bit 5
DIF_13 Output Control RW Hi-Z Enable 1
Bit 4
DIF_12 Output Control R
Hi-Z Enable 1
Bit 3
DIF_11 Output Control RW Hi-Z Enable 1
Bit 2
DIF_10 Output Control RW Hi-Z Enable 1
Bit 1
DIF_9 Output Control RW Hi-Z Enable 1
Bit 0
DIF_8 Output Control RW Hi-Z Enable 1
SMBusTable: Output Enable Readback Register
Pin # Name Control Function T
e0 1PWD
Bit 7
OE11# Input Pin Readback
R
Pin Low Pin Hi X
Bit 6
OE10# Input Pin Readback
R
Pin Low Pin Hi X
Bit 5
OE9# Input Pin Readback
R
Pin Low Pin Hi X
Bit 4
OE8# Input Pin Readback
R
Pin Low Pin Hi X
Bit 3
OE7# Input Pin Readback
R
Pin Low Pin Hi X
Bit 2
OE6# Input Pin Readback
R
Pin Low Pin Hi X
Bit 1
OE5# Input Pin Readback
R
Pin Low Pin Hi X
Bit 0
OE_01234# Input Pin Readback
R
Pin Low Pin Hi X
RESERVED
B
te 0
B
te 2
-
-
B
te 1
PLL_BW# adjust
BYPASS# test mode / PLL
-
4
59
56
2
5
B
te 3
72
36
52
49
00 = Low BW (1MHz)
10 = Bypass
11 = High BW (3MHz)
See Frequency Select
Table
