TC74VHC138F/FT/FK
2014-03-01
1
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHC138F, TC74VHC138FT, TC74VHC138FK
3-to-8 Line Decoder
The TC74VHC138 is an advanced high speed CMOS 3-to-8
DECODER fabricated with silicon gate C
2
MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
When the device is enabled, 3 Binary Select inputs (A, B and C)
determine which one of the outputs (
0Y-7Y ) will go low.
When enable input G1 is held low or either
2AG or 2BG is held
high, decoding function is inhibited and all outputs go high.
G1,
2AG , and 2BG inputs are provided to ease cascade
connection and for use as an address decoder for memory
systems.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
Features
• High speed: t
pd
= 5.7 ns (typ.) at V
CC
= 5 V
• Low power dissipation: I
CC
= 4 μA (max) at Ta = 25°C
• High noise immunity: V
NIH
= V
NIL
= 28% V
CC (min)
• Power down protection is provided on all inputs.
• Balanced propagation delays: t
pLH
∼
−
t
pHL
• Wide operating voltage range: V
CC (opr)
= 2 V to 5.5 V
• Pin and function compatible with 74ALS138
Weight
SOP16-P-300-1.27A : 0.18 g (typ.)
TSSOP16-P-0044-0.65A : 0.06 g (typ.)
VSSOP16-P-0030-0.50 : 0.02 g (typ.)
TC74VHC138F
TC74VHC138FT
TC74VHC138FK
Start of commercial production
1991-11
