ACPL-074L-000E

7
0.001
0.01
0.1
1
10
100
1000
1.1 1.2 1.3 1.4 1.5 1.6
V
F
-FORWARD VOLTAGE-V
I
F
-FORWARD CURRENT-mA
I
F
V
F
T
A
=25°C
0
2
4
6
8
10
12
-40 -20 0 20 40 60 80 100
T
A
-TEMPERATURE-
o
C
I
DDH
-LOGIC HIGH OUTPUT SUPPLY CURRENT -mA
V
DD
=5.0V
V
DD
=3.3V
0
1
2
3
4
5
6
-40 -20 0 20 40 60 80 100 120
T
A
-TEMPERATURE-
o
C
I
th
-INPUT THRESHOLD CURRENT-mA
5V
3.3V
I
oL
=20uA
0
2
4
6
8
10
12
-40 -20 0 20 40 60 80 100
T
A
-TEMPERATURE-
o
C
I
DDl
-LOGIC LOW OUTPUT SUPPLY CURRENT-mA
V
DD
=5.0V
V
DD
=3.3V
Figure 1. Typical input diode forward characteristic.
Figure 2. Typical input threshold current vs. temperature.
Figure 3. Typical logic high O/P supply current vs. temperature for ACPL-074L. Figure 4. Typical logic low O/P supply current vs. temperature for ACPL-074L.
Package Characteristics
All Typical at T
A
= 25°C.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Input-Output Insulation I
I-O
1.0 µA 45% RH, t = 5 s
V
I-O
= 3 kV DC,
T
A
= 25°C
Input-Output Momentary
Withstand Voltage
V
ISO
3750 Vrms RH ≤ 50%, t = 1 min.,
T
A
= 25°C
Input-Output Resistance R
I-O
10
12
W
V
I-O
= 500 V dc
Input-Output Capacitance C
I-O
0.6 pF f = 1 MHz, T
A
= 25°C
Notes:
1. Slew rate of supply voltage ramping is recommended to ensure no glitch more than 1V to appear at the output pin.
2. t
PHL
propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level of the falling edge of the V
O
signal.
t
PLH
propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the rising edge of the V
O
signal.
3. PWD is dened as |t
PHL
- t
PLH
|.
4. t
PSK
is equal to the magnitude of the worst case dierence in t
PHL
and/or t
PLH
that will be seen between units at any given temperature within the
recommended operating conditions.
5. CM
H
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
6. CM
L
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
8
0
5
10
15
20
25
30
35
40
45
50
6 7 8 9 10 11 12 13 14 15 16
I
F
– PULSE INPUT CURRENT – mA
t
p
– PROPAGATION DELAY; PWD-PULSE WIDTH
DISTORTION – ns
T
PHL
CH1
T
PHL
CH2
T
PLH
CH1
T
PLH
CH2
PWD CH1 PWD CH2
V
DD
=5V
T
A
=25°C
0
5
10
15
20
25
30
35
40
45
50
6 7 8 9 10 11 12 13 14 15 16
I
F
– PULSE INPUT CURRENT – mA
t
p
– PROPAGATION DELAY; PWD-PULSE WIDTH
DISTORTION – ns
T
PHL
CH1
T
PHL
CH2
T
PLH
CH1
T
PLH
CH2
PWD CH1
PWD CH2
V
DD
=3.3V
T
A
=25°C
1.35
1.4
1.45
1.5
1.55
1.6
1.65
-40 -20 0 20 40 60 80 100
T
A
-TEMPERATURE-
o
C
V
F
-FORWARD VOLTAGE-V
Figure 8. Recommended printed circuit board layout
GND1
7
5
6
8
2
3
4
1
GND2
C
NC
V
DD
V
O
I
F
XXX
YWW
7
5
6
8
2
3
4
1
GND 2
C
V
DD
GND 1
XXX
YWW
V
O2
V
O1
I
F1
GND 1
I
F2
ACPL-071L ACPL-074L
C = 0.01mF to 0.1mF
Figure 5. Typical switching speed vs. pulse input current at 5V supply voltage.
Figure 6. Typical switching speed vs. pulse input current at 3.3V supply
voltage.
Application Information
Bypassing and PC Board Layout
The ACPL-071L and ACPL-074L optocouplers are extreme-
ly easy to use. ACPL-071L and ACPL-074L provide CMOS
logic output due to the high-speed CMOS IC technology
used.
The external components required for proper operation
are the input limiting resistor and the output bypass ca-
pacitor. Capacitor values should be between 0.01 µF and
0.1 µF.
For each capacitor, the total lead length between both
ends of the capacitor and the power-supply pins should
not exceed 20 mm.
Figure 7 Typical V
F
vs. temperature.
9
Propagation Delay, Pulse-Width Distortion and Propa-
gation Delay Skew
Propagation delay is a gure of merit which describes how
quickly a logic signal propagates through a system. The
propagation delay from low to high (t
PLH
) is the amount
of time required for an input signal to propagate to the
output, causing the output to change from low to high.
Similarly, the propagation delay from high to low (t
PHL
) is
the amount of time required for the input signal to propa-
gate to the output, causing the output to change from
high to low (see Figure 9).
Pulse-width distortion (PWD) results when t
PLH
and t
PHL
dier in value. PWD is dened as the dierence between
t
PLH
and t
PHL
and often PWD is dened as the dierence
between t
PLH
and t
PHL
and often determines the maxi-
mum data rate capability of a transmission system. PWD
can be expressed in percent by dividing the PWD (in ns)
by the minimum pulse width (in ns) being transmitted.
Typically, PWD on the order of 20-30% of the minimum
pulse width is tolerable; the exact gure depends on the
particular application (RS232, RS422, T-1, etc.).
Propagation delay skew, t
PSK
, is an important parameter
to consider in parallel data applications where synchroni-
zation of signals on parallel data lines is a concern.
If the parallel data is being sent through a group of opto-
couplers, dierences in propagation delays will cause the
data to arrive at the outputs of the optocouplers at dier-
ent times. If this dierence in propagation delays is large
enough, it will determine the maximum rate at which par-
allel data can be sent through the optocouplers.
Propagation delay skew is dened as the dierence be-
tween the minimum and maximum propagation delays,
either t
PLH
or t
PHL
, for any given group of optocouplers
which are operating under the same conditions (i.e., the
same supply voltage, output load, and operating temper-
ature). As illustrated in Figure 10, if the inputs of a group of
optocouplers are switched either ON or OFF at the same
time, t
PSK
is the dierence between the shortest propaga-
tion delay, either t
PLH
or t
PHL
, and the longest propagation
delay, either t
PLH
or t
PHL
. As mentioned earlier, t
PSK
can de-
termine the maximum parallel data transmission rate.
Figure 10 is the timing diagram of a typical parallel data
application with both the clock and the data lines being
sent through optocouplers. The gure shows data and
clock signals at the inputs and outputs of the optocou-
plers. To obtain the maximum data transmission rate, both
edges of the clock signal are being used to clock the data;
if only one edge were used, the clock signal would need
to be twice as fast.
Propagation delay skew represents the uncertainty of
where an edge might be after being sent through an opt-
ocoupler. Figure 10 shows that there will be uncertainty in
both the data and the clock lines. It is important that these
two areas of uncertainty not overlap, otherwise the clock
signal might arrive before all of the data outputs have
settled, or some of the data outputs may start to change
before the clock signal has arrived.
From these considerations, the absolute minimum pulse
width that can be sent through optocouplers in a parallel
application is twice t
PSK
. A cautious design should use a
slightly longer pulse width to ensure that any additional
uncertainty in the rest of the circuit does not cause a
problem.
DATA
INPUTS
CLOCK
DATA
OUTPUTS
CLOCK
t
PSK
t
PSK
50%
50%
t
PSK
I
F
V
O
I
F
V
O
50%,
CMOS
50%,
CMOS
Figure 9. Propagation delay and skew waveform
Figure 10. Parallel data transmission example

ACPL-074L-000E

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
High Speed Optocouplers Digital Optocouplers
Lifecycle:
New from this manufacturer.
Delivery:
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