V
O
PULSE
GEN.
Z = 50 Ω
t = 5 ns
O
r
I MONITOR
F
I
F
0.1 µF
L
R
C
L
= 15 pF*
R
M
0
t
PHL
t
PLH
O
V
I
F
OL
V
1.5 V 1.5 V
5 V
+5 V
7
1
2
3
4
5
6
8
10% DUTY CYCLE
I/f < 100 µs
(SATURATED
RESPONSE)
t
f
t
r
O
V
(NON-SATURATED
RESPONSE)
5 V
90%
10%
90%
10%
* INCLUDES PROBE AND
FIXTURE CAPACITANCE
V
O
I
F
L
R
A
B
PULSE GEN.
V
CM
+
V
FF
O
V
OL
V
O
V
0 V
10%
90% 90%
10%
SWITCH AT A: I = 0 mA
F
SWITCH AT B: I = 1.6 mA
F
CM
V
t
r
t
f
5 V
+5 V
–
7
1
2
3
4
5
6
8
R
CC
(SEE NOTE 6)
10 V
t
r
, t
f
= 16 ns
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2015 Avago Technologies. All rights reserved. Obsoletes AV01-0543EN
AV02-1359EN - March 4, 2015
Figure 12. Switching test circuit
Figure 11. Thermal derating curve, dependence of safety limiting value
with case temperature per IEC/EN/DIN EN 60747-5-5
Figure 10. Logic low supply current vs. forward current
Figure 13. Test circuit for transient immunity and typical waveforms
0.8
0.6
0.4
0.2
0 4
8 10
16
I
CCL
– LOGIC LOW SUPPLY CURRENT – mA
I
F
– FORWARD CURRENT
12 14
6
2
0
V
CC
= 18 V
0.1
0.3
0.5
0.7
V
CC
= 5 V
OUTPUT POWER – P
S
, INPUT CURRENT – I
S
0
0
T
S
– CASE TEMPERATURE – °C
175
1000
50
400
12525 75 100 150
600
800
200
100
300
500
700
900
P
S
(mW)
I
S
(mA)
WIDEBODY
