10
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
V-
TRANSISTOR COUNT:
ISL84521: 188
ISL84522: 188
ISL84523: 188
PROCESS:
Si Gate CMOS
FIGURE 15. FREQUENCY RESPONSE
FIGURE 16. CROSSTALK AND OFF ISOLATION
Typical Performance Curves T
A
= 25
o
C, Unless Otherwise Specified (Continued)
FREQUENCY (MHz)
3
0
-3
NORMALIZED GAIN (dB)
0
45
90
135
180
PHASE (DEGREES)
1 10 100 600
V
IN
= 5V
P-P
V
IN
= 5V
P-P
V
IN
= 0.2V
P-P
V
IN
= 0.2V
P-P
GAIN
PHASE
V
S
= 5V
R
L
= 50
FREQUENCY (Hz)
1k 100k 1M 100M 500M10k 10M
-110
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
CROSSTALK (dB)
OFF ISOLATION (dB)
110
10
20
30
40
50
60
70
80
90
100
ISOLATION
CROSSTALK
V
S
= 2V to 5V
V+ = 3V to 12V or
R
L
= 50
ISL84521, ISL84522, ISL84523
11
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com
.
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE REVISION CHANGE
August 10, 2015 FN6031.4 Updated Ordering Information table on page 2.
Added Revision History and About Intersil sections.
Updated Package Outline Drawing (POD) M16.173 with the latest version. Changes from Rev. 1 to Rev 2
are as follows:
-Convert to new POD format by moving dimensions from table onto drawing and adding land pattern. No
dimension changes.
ISL84521, ISL84522, ISL84523
12
ISL84521, ISL84522, ISL84523
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AM BS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H
0.25(0.010) BM M
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.3859 0.3937 9.80 10.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N16 167
-
Rev. 1 6/05

ISL84523IBZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Analog Switch ICs SWITCH 4X SPST 3V MIX 16N IND
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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