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74HC4094PW-Q100J

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
74HC_HCT4094_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 30 January 2013 9 of 21
NXP Semiconductors
74HC4094-Q100; 74HCT4094-Q100
8-stage shift-and-store bus register
t
W
pulse width CP HIGH or LOW;
see Figure 8
V
CC
= 2.0 V 80 14 - 100 - 120 - ns
V
CC
= 4.5 V 16 5 - 20 - 24 - ns
V
CC
= 6.0 V 14 4 - 17 - 20 - ns
STR HIGH; see Figure 9
V
CC
= 2.0 V 80 14 - 100 - 120 - ns
V
CC
= 4.5 V 16 5 - 20 - 24 - ns
V
CC
= 6.0 V 14 4 - 17 - 20 - ns
t
su
set-up time D to CP; see Figure 10
V
CC
= 2.0 V 50 14 - 65 - 75 - ns
V
CC
= 4.5 V 10 5 - 13 - 15 - ns
V
CC
= 6.0 V 9 4 - 11 - 13 - ns
CP to STR; see Figure 9
V
CC
= 2.0 V 100 28 - 125 - 150 - ns
V
CC
= 4.5 V 20 10 - 25 - 30 - ns
V
CC
= 6.0 V 17 8 - 21 - 26 - ns
t
h
hold time D to CP; see Figure 10
V
CC
= 2.0 V 3 -6 - 3 - 3 - ns
V
CC
= 4.5 V 3 -2 - 3 - 3 - ns
V
CC
= 6.0 V 3 -2 - 3 - 3 - ns
CP to STR; see Figure 9
V
CC
= 2.0 V 0 -14 - 0 - 0 - ns
V
CC
= 4.5 V 0 -5 - 0 - 0 - ns
V
CC
= 6.0 V 0 -4 - 0 - 0 - ns
f
max
maximum
frequency
CP; see Figure 8
V
CC
= 2.0 V 6.0 28 - 4.8 - 4.0 - MHz
V
CC
= 4.5 V 30 87 - 24 - 20 - MHz
V
CC
=5V; C
L
=15pF - 95 - - - - - MHz
V
CC
= 6.0 V 35 103 - 28 - 24 - MHz
C
PD
power
dissipation
capacitance
C
L
= 50 pF; f = 1 MHz;
V
I
=GNDtoV
CC
[5]
-83- - - - -pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC_HCT4094_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 30 January 2013 10 of 21
NXP Semiconductors
74HC4094-Q100; 74HCT4094-Q100
8-stage shift-and-store bus register
[1] t
pd
is the same as t
PLH
and t
PHL
.
74HCT4094-Q100
t
pd
propagation
delay
CP to QS1; see Figure 8
[1]
V
CC
= 4.5 V - 23 39 - 49 - 59 ns
V
CC
=5V; C
L
=15pF - 19 - - - - - ns
CP to QS2; see Figure 8
[1]
V
CC
= 4.5 V - 21 36 - 45 - 54 ns
V
CC
=5V; C
L
=15pF - 18 - - - - - ns
CP to QPn; see Figure 8
[1]
V
CC
= 4.5 V - 25 43 - 54 - 65 ns
V
CC
=5V; C
L
=15pF - 21 - - - - - ns
STR to QPn; see Figure 9
[1]
V
CC
= 4.5 V - 22 39 - 49 - 59 ns
V
CC
=5V; C
L
=15pF - 19 - - - - - ns
t
en
enable time OE to QPn; see Figure 11
[2]
V
CC
= 4.5 V - 20 35 - 44 - 53 ns
t
dis
disable time OE to QPn; see Figure 11
[3]
V
CC
= 4.5 V - 21 35 - 44 - 53 ns
t
t
transition
time
QPn and QSn; see
Figure 8
[4]
V
CC
= 4.5 V - 7 15 - 19 - 22 ns
t
W
pulse width CP HIGH or LOW;
see Figure 8
V
CC
= 4.5 V 16 7 - 20 - 24 - ns
STR HIGH; see Figure 9
V
CC
= 4.5 V 16 5 - 20 - 24 - ns
t
su
set-up time Dn to CP; see Figure 10
V
CC
= 4.5 V 10 4 - 13 - 15 - ns
CP to STR; see Figure 9
V
CC
= 4.5 V 20 9 - 25 - 30 - ns
t
h
hold time Dn to CP; see Figure 10
V
CC
= 4.5 V 4 0 - 4 - 4 - ns
CP to STR; see Figure 9
V
CC
= 4.5 V 0 4- 0 - 0 - ns
f
max
maximum
frequency
CP; see Figure 8
V
CC
= 4.5 V 30 80 - 24 - 20 - MHz
V
CC
=5V; C
L
=15pF - 86 - - - - - MHz
C
PD
power
dissipation
capacitance
C
L
= 50 pF; f = 1 MHz;
V
I
=GNDtoV
CC
[5]
-92- - - - -pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC_HCT4094_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 30 January 2013 11 of 21
NXP Semiconductors
74HC4094-Q100; 74HCT4094-Q100
8-stage shift-and-store bus register
[2] t
en
is the same as t
PZH
and t
PZL
.
[3] t
dis
is the same as t
PLZ
and t
PHZ
.
[4] t
t
is the same as t
THL
and t
TLH
.
[5] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
12. Waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 8. Propagation delay input (CP) to output (QPn, QS1, QS2), output transition time, clock input (CP) pulse
width and the maximum frequency (CP)
I
PD[
W
:
W
3+/
W
3/+
9
,
*1'
9
2+
9
2/
43Q46RXWSXW
&3LQSXW
9
0
9
0


DDD
W
3+/
W
3/+
W
7/+
W
7+/
9
2+
9
2/
46RXWSXW
9
0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

74HC4094PW-Q100J

Mfr. #:
Buy 74HC4094PW-Q100J
Manufacturer:
Nexperia
Description:
Counter Shift Registers 74HC4094PW-Q100/TSSOP16/REEL 1
Lifecycle:
New from this manufacturer.
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