74ABT821 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 7 November 2011 7 of 16
NXP Semiconductors
74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
10. Dynamic characteristics
11. Waveforms
Table 7. Dynamic characteristics
GND = 0 V; for test circuit, see Figure 8.
Symbol Parameter Conditions 25 C; V
CC
= 5.0 V 40 C to +70 C;
V
CC
= 5.0 V 0.5 V
Unit
Min Typ Max Min Max
t
PLH
LOW to HIGH
propagation delay
CP to Qn; see Figure 5 2.1 4.1 5.6 2.1 6.2 ns
t
PHL
HIGH to LOW
propagation delay
CP to Qn; see Figure 5 2.8 4.6 6.2 2.8 6.7 ns
t
PZH
OFF-state to HIGH
propagation delay
OEn to Qn; see Figure 6 1.0 3.0 4.5 1.0 5.3 ns
t
PZL
OFF-state to LOW
propagation delay
OEn to Qn; see Figure 6 2.2 4.1 5.6 2.2 6.3 ns
t
PHZ
HIGH to OFF-state
propagation delay
OEn to Qn; see Figure 6 2.7 4.7 6.2 2.7 6.7 ns
t
PLZ
LOW to OFF-state
propagation delay
OEn to Qn; see Figure 6 2.3 4.6 6.1 2.3 6.5 ns
t
su(H)
set-up time HIGH Dn to CP; see Figure 7 2.1 0.5 - 2.1 - ns
t
su(L)
set-up time LOW Dn to CP; see Figure 7 2.1 0.3 - 2.1 - ns
t
h(H)
hold time HIGH Dn to CP; see Figure 7 1.3 0 - 1.3 - ns
t
h(L)
hold time LOW Dn to CP; see Figure 7 1.3 0.3 - 1.3 - ns
t
WH
pulse width HIGH CP; see Figure 5 2.9 1.8 - 2.9 - ns
t
WL
pulse width LOW CP; see Figure 5 3.8 2.8 - 3.8 - ns
f
max
maximum
frequency
see Figure 5 125 185 - 125 - MHz
V
M
= 1.5 V
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 5. Propagation delay clock input (CP) to output (Qn), clock pulse (CP) width and
maximum clock (CP) frequency
001aac445
CP
input
Qn
output
t
PHL
t
PLH
t
WH
t
WL
1 / f
max
V
M
V
OH
V
I
GND
V
OL
V
M
