ST1284-03A8RL

Application information ST1284
4/9 DocID6976 Rev 5
Figure 4. Functional diagram
2 Application information
The functional diagram here above presents a IEEE1284-A connector pinout and show how
to connect the ST1284 in order to correctly terminate and filter the 17 signal lines. The
IEEE1284-A connector is the PC standard for the host connection.
Control and status lines (from 10 to 17) only require a pull-up resistor (R
p
) and a filter
capacitor (C).
The data lines (from 2 to 9) and the strobe (pin 1) also require a termination series resistor
(R
s
) in addition to the pull-up resistor and a filter capacitor. The V
CC
is connected to pin 20
and the ground to pin 22.
The ST1284 can be used with all 3 types of connectors defined in the IEEE1284 standard:
IEEE1284-A is a DB 25 connector which is the PC standard for the host connection.
IEEE1284-B is a 36 pin, 0.085 inch center line connector used on the peripheral
device.
IEEE1284-C is a new 36 pin, 0.050 inch center line connector which can be used for
both host and peripherals.
14 Autofeed
15 Error
16 Reset
17 Select in
1 Strobe
2 Bit 1
3 Bit 2
4 Bit 3
5 Bit 4
6 Bit 5
7 Bit 6
8 Bit 7
9 Bit 8
13 Select paper
14
1
13
25
1
28
2
27
20
26
25
24
23
21
19
18
17
16
3
4
5
6
7
9
11
13
14
8
10
12
15
22
10 Acknowledge
11 Busy
12 Paper Out
Vcc
Vcc
Vcc
Gnd
ST1284-xxA8
DocID6976 Rev 5 5/9
ST1284 Technical information
9
3 Technical information
3.1 Frequency behavior of data and strobe signals
3.2 ESD protection
In addition to the requirements of termination and EMC compatibility, computing devices are
required to be tested for ESD susceptibility. This test is described in the IEC 61000-4-2. This
test requires that a device tolerates ESD events and remain operational without user
intervention.
The ST1284 is particularly optimized to perform ESD protection. ESD protection is based on
the use of device which clamps at:
V
ouput
= V
BR
+ R
d
· I
PP
This protection function is split in 2 stages. As shown in Figure 7, the ESD strikes are
clamped by the first stage S
1
and then its remaining overvoltage is applied to the second
stage through the resistor R. Such a configuration makes the voltage very low at the output.
Figure 7. ST1284 ESD clamping behavior
Figure 5. Measurement conditions Figure 6. S21 typical frequency response
curve for data and strobe signals
ST1284
SPECTRUM
ANALYSER
TRACKING
GENERATOR
Vg
VoutVin
50
Ω
50
Ω
+5V
1 3 10 30 100 300 1,000
-30.00
-25.00
-20.00
-15.00
-10.00
-5.00
0.00
dB
F (MHz)
ESD Surge
Vinput
Voutput
Rload
Rg
R
S1
Rd
V
BR
V
BR
Device
to be
protected
ST1284-xxA8
Rd
S2
Technical information ST1284
6/9 DocID6976 Rev 5
To have a good approximation of the remaining voltages at both V
in
and V
out
stages, we give
the typical dynamic resistance value R
d
.
Taking into account these hypothesis R
t
>R
d
, R
g
>R
d
and R
load
>R
d
, gives these formulas:
The results of the calculation done for V
PP
= 8 kV, R
g
= 330 Ω (IEC 61000-4-2 standard),
V
BR
= 7 V (typ.) and R
d
= 1 Ω (typ.) give:
V
input
= 31.2 V
V
output
= 7.95 V
This confirms the very low remaining voltage across the device to be protected. It is also
important to note that in this approximation the parasitic inductance effect was not taken into
account. This could be few tenths of volts during few ns at the input side. This parasitic
effect is not present at the output side due to the low current involved after the resistance R.
The measurements in Figure 9 clearly show the high efficiency of the ESD protection:
No influence of the parasitic inductances on V
out
stage
V
output
clamping voltage very close to V
BR
(positive strike) and -V
F
(negative strike)
Figure 8. Measurement conditions
Figure 9. Remaining voltage at the input and output of the device during a ±16 kV ESD
surge (IEC 61000-4-2)
V
output
=
R
t
· V
BR
+ R
d
· V
input
R
t
ST1284
Vinput Voutput
ESD
SURGE

ST1284-03A8RL

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Interface - Specialized Parallel Port Term
Lifecycle:
New from this manufacturer.
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