6.42
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
13
Timing Waveform of Write with Port-to-Port Read and BUSY
(2,5)
(M/S = VIH)
(4)
Timing Waveform of Write with BUSY
NOTES:
1. t
WH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on Port "B", blocking R/W
"B", until BUSY"B" goes HIGH.
3. t
WB is only for the 'Slave' Version.
2739 drw 13
t
DW
t
APS
(1)
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
2739 drw 14
R/W
"A"
BUSY
"B"
t
WP
t
WB
(3)
R/W
"B"
t
WH
(1)
(2)
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS is ignored for M/S = VIL (SLAVE).
2. CE
L = CER = VIL
3. OE = VIL for the reading port.
4. If M/S = V
IL(slave) then BUSY is input (BUSY"A" = VIH) and BUSY"B" = "don't care", for this example.
5. All timing is the same for left and right port. Port "A' may be either left or right port. Port "B" is the port opposite from Port "A".
