72V71660DR Datasheet 72V71660DRG, 72V71660BBG, 72V71660DR | P7-P9

INDUSTRIAL TEMPERATURE RANGE

IDT72V71660 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 16,384 x 16,384

TABLE 4 — INTERNAL REGISTER AND ADDRESS MEMORY MAPPING

TABLE 3 — OUTPUT HIGH-IMPEDANCE CONTROL

TABLE 1 — CONSTANT THROUGHPUT

DELAY VALUE

TABLE 2 — VARIABLE THROUGHPUT

DELAY VALUE

NOTE: Unused STA and CH bits should be set to zero.

Delay for Constant Throughput Delay Mode

Input Rate (m – output channel number)

(n – input channel number)

2.048Mb/s 32 + (32 – n) +m time-slots

4.096Mb/s 64 + (64 – n) +m time-slots

8.192Mb/s 128 + (128 – n) +m time-slots

16.384Mb/s 256 + (256 – n) +m time-slots

Delay for Variable Throughput Delay Mode

Input Rate (m – output channel number; n – input channel number)

≤≤

≤ n+2 m > n+2

2.048Mb/s 32 – (n-m) time-slots (m-n) time-slots

4.096Mb/s 64 – (n-m) time-slots (m-n) time-slots

8.192Mb/s 128 – (n-m) time-slots (m-n) time-slots

16.384Mb/s 256 – (n-m) time-slots (m-n) time-slots

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 R/W Location

1 1 STA5 STA4 STA3 STA2 STA1 STA0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 R Data Memory

1 0 STA5 STA4 STA3 STA2 STA1 STA0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 R/W Connection Memory

0100000xxxxxxxxxR/WControl Register

0100001xxxxxxxxxRFrame Align Register

0110000xxxxxxxxxR/W Frame Offset Register 0

0110001xxxxxxxxxR/W Frame Offset Register 1

0110010xxxxxxxxxR/W Frame Offset Register 2

0110011xxxxxxxxxR/W Frame Offset Register 3

0110100xxxxxxxxxR/W Frame Offset Register 4

0110101xxxxxxxxxR/W Frame Offset Register 5

0110110xxxxxxxxxR/W Frame Offset Register 6

0110111xxxxxxxxxR/W Frame Offset Register 7

0111000xxxxxxxxxR/W Frame Offset Register 8

0111001xxxxxxxxxR/W Frame Offset Register 9

0111010xxxxxxxxxR/W Frame Offset Register 10

0111011xxxxxxxxxR/W Frame Offset Register 11

0111100xxxxxxxxxR/W Frame Offset Register 12

0111101xxxxxxxxxR/W Frame Offset Register 13

0111110xxxxxxxxxR/W Frame Offset Register 14

0111111xxxxxxxxxR/W Frame Offset Register 15

Bits MOD1-0 Values in ODE pin OSB bit in Control Output Status

Connection Memory Register

1 and 1 Don’t Care Don’t Care Per-channel

high-Impedance

Any, other than 1 and 1 0 0 high-Impedance

Any, other than 1 and 1 0 1 Enable

Any, other than 1 and 1 1 0 Enable

Any, other than 1 and 1 1 1 Enable

INDUSTRIAL TEMPERATURE RANGE

IDT72V71660 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 16,384 x 16,384

TABLE 5 — CONTROL REGISTER (CR) BITS

Reset Value: 0000H.

BIT NAME DESCRIPTION

15 SRS A one will reset the device and have the same effect as the RESET pin. Must be zero for normal operation.

(Software Reset)

14 OEI When 1, the TX32-63/OEI0-31 pins will be OEI0-31 and reflect the active or high-impedance state of their corresponding output data

(Output Enable Indication) streams. When 0, this feature is disabled and these pins are used as output data streams TX32-63.

13 OEPOL When 1, a one on an Output Enable Indication pin denotes an active state on the output data stream; zero on an Output Enable Indication

(Output Enable Polarity) pin denotes high-impedance state. When 0, a one on an Output Enable Indication pin denotes high-impedance and a zero denotes

an active state.

12 AOE When 1, TX0-63 will behave as OEI0-63 accordingly. These outputs will reflect the active or high-impedance state of the

(All Output Enables) corresponding output data streams (TX0-63) in another IDT72V71660 if programmed identically. When 0, the TSI operates in the normal

switch mode.

11-10 Unused Must be zero for normal operation.

9 MBP When 1, the Connection Memory block programming feature is ready for the programming of Connection Memory HIGH bits,

(Memory Block Program) bit 14 and bit 15. When 0, this feature is disabled.

8-7 BPD1-0 These bits carry the value to be loaded into the Connection Memory block whenever the memory block programming feature

(Block Programming is activated. After the Memory Block Program bit in the Control Register is set to 1 and the Block Programming Enable is set to 1,

Data) the contents of the bits Block Programming Data1-0 are loaded into bit 15 and 14 of the Connection Memory. Bit 13 to bit 0 of the

Connection Memory are set to 0.

6 BPE A zero to one transition of this bit enables the memory block programming function. Once the Block Programming Enable

(Begin Block bit is set HIGH, the device requires two frames to complete the block programming. After the programming function has finished,

Programming Enable) the Block Programming Enable, Memory Block Program and Block Programming Data1-0 bits will be reset to zero by the device

to indicate the operation is complete.

5 OSB When ODE = 0 and Output Stand By = 0, the output drivers of the transmit serial streams are in high-impedance mode. When

(Output Stand By) either ODE = 1 or Output Stand By =1 the output serial streams drivers function normally.

4 S FE A zero to one transition in this bit starts the Frame Evaluation procedure. When the Complete Frame Evaluation bit in the Frame Alignment

(Start Frame Evaluation) Register changes from zero to one, the evaluation procedure stops. To start another Frame Evaluation cycle, set this bit to zero for

at least one frame.

3-2 Unused Must be zero for normal operation.

1-0 DR1-0 DR1 DR0 Data Rate Master Clock

(Data Rate Select) 0 0 2.048Mb/s 4.096 MHz

0 1 4.096Mb/s 8.192 MHz

1 0 8.192Mb/s 16.384 MHz

1 1 16.384Mb/s 16.384 MHz

1514131211109876543210

SRS OEI OEPOL AOE 0 0 MBP BPD1 BPD0 BPE OSB SFE 0 0 DR1 DR0

INDUSTRIAL TEMPERATURE RANGE

IDT72V71660 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 16,384 x 16,384

TABLE 6 — CONNECTION MEMORY BITS

NOTE:

1. Unused Source Stream Address Bits and Source Chan-

nel Address Bits bits should be set to zero.

1514131211109876543210

MOD1 MOD0 SAB5 SAB4 SAB3 SAB2 SAB1 SAB0 CAB7 CAB6 CAB5 CAB4 CAB3 CAB2 CAB1 CAB0

Bit Name Description

15, 14 MOD1-0 MOD1 MOD0 MODE

(Switching Mode Selection) 0 0 Variable Delay mode

0 1 Constant Delay mode

1 0 Processor mode

1 1 Output high-impedance

13-8 SAB5-0 The binary value is the number of the data stream for the source of the connection.

(Source Stream Address Bits)

7-0 CAB7-0 The binary value is the number of the channel for the source of the connection.

(Source Channel Address Bits)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P31

72V71660DR

Mfr. #:

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Manufacturer:

IDT

Description:

Digital Bus Switch ICs 3.3V 16KX16K TSI SWITCH

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72V71660DR

72V71660DR

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