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OUTPUT DATA FORMAT
The AR0130 image data is read out in a progressive scan.
Valid image data is surrounded by horizontal and vertical
blanking (see Figure 8). The amount of horizontal row time
(in clocks) is programmable through R0x300C. The amount
of vertical frame time (in rows) is programmable through
R0x300A. LINE_VALID (LV) is HIGH during the shaded
region of Figure 8. Optional Embedded Register setup
information and Histogram statistic information are
available in first 2 and last row of image data.
Figure 8. Spatial Illustration of Image Readout
P
0,0
P
0,1
P
0,2
.....................................P
0,n1
P
0,n
P
1,0
P
1,1
P
1,2
.....................................P
1,n1
P
1,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
P
m1,0
P
m1,1
.....................................P
m1,n1
P
m1,n
P
m,0
P
m,1
.....................................P
m,n1
P
m,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
VALID IMAGE
HORIZONTAL
BLANKING
VERTICAL BLANKING
VERTICAL/HORIZONTAL
BLANKING
Readout Sequence
Typically, the readout window is set to a region including
only active pixels. The user has the option of reading out
dark regions of the array, but if this is done, consideration
must be given to how the sensor reads the dark regions for
its own purposes.
Parallel Output Data Timing
The output images are divided into frames, which are
further divided into lines. By default, the sensor produces
968 rows of 1288 columns each. The FV and LV signals
indicate the boundaries between frames and lines,
respectively. PIXCLK can be used as a clock to latch the
data. For each PIXCLK cycle, with respect to the falling
edge, one 12bit pixel datum outputs on the D
OUT pins.
When both FV and LV are asserted, the pixel is valid.
PIXCLK cycles that occur when FV is deasserted are called
vertical blanking. PIXCLK cycles that occur when only LV
is deasserted are called horizontal blanking.
Figure 9. Default Pixel Output Timing
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LV and FV
The timing of the FV and LV outputs is closely related to
the row time and the frame time.
FV will be asserted for an integral number of row times,
which will normally be equal to the height of the output
image.
LV will be asserted during the valid pixels of each row.
The leading edge of LV will be offset from the leading edge
of FV by 6 PIXCLKs. Normally, LV will only be asserted if
FV is asserted; this is configurable as described below.
LV Format Options
The default situation is for LV to be deasserted when FV
is deasserted. By configuring R0x306E[1:0], the LV signal
can take two different output formats. The formats for
reading out four lines and two vertical blanking lines are
shown in Figure 10.
Figure 10. LV Format Options
Default
Continuous LV
FV
LV
FV
LV
The timing of an entire frame is shown in Figure 11: “Line
Timing and FRAME_VALID/LINE_VALID Signals”.
Frame Time
The pixel clock (PIXCLK) represents the time needed to
sample 1 pixel from the array. The sensor outputs data at the
maximum rate of 1 pixel per PIXCLK. One row time (t
ROW
)
is the period from the first pixel output in a row to the first
pixel output in the next row. The row time and frame time are
defined by equations in Table 4.
Figure 11. Line Timing and FRAME_VALID/LINE_VALID Signals
Table 4. FRAME TIME (Example Based on 1280 x 960, 45 Frames Per Second)
Parameter Name Equation Timing at 74.25 MHz
A Active data time Context A: R0x3008 R0x3004 + 1
Context B: R0x308E R0x308A + 1
1280 pixel clocks
= 17.23
ms
P1 Frame start blanking 6 (fixed) 6 pixel clocks
= 0.08
ms
P2 Frame end blanking 6 (fixed) 6 pixel clocks
= 0.08
ms
Q Horizontal blanking R0x300C A 370 pixel clocks
= 4.98 ms
A+Q (t
ROW
) Line (Row) time R0x300C 1650 pixel clocks
= 22.22 ms
V Vertical blanking Context A: (R0x300A(R0x3006R0x3002+1)) x (A + Q)
Context B: ((R0x30AA(R0x3090R0x308C+1)) x (A + Q)
49,500 pixel clocks
= 666.66 ms
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Table 4. FRAME TIME (Example Based on 1280 x 960, 45 Frames Per Second)
Parameter Timing at 74.25 MHzEquationName
Nrows x (t
ROW
) Frame valid time Context A: ((R0x3006R0x3002+1)*(A+Q))Q+P1+P2
Context B: ((R0x3090R0x308C+1)*(A+Q))Q+P1+P2
1,583,642 pixel clocks
= 21.33 ms
F Total frame time V + (Nrows x (A + Q)) 1,633,500 pixel clocks
= 22.22 ms
Sensor timing is shown in terms of pixel clock cycles (see
Figure 8). The recommended pixel clock frequency is
74.25 MHz. The vertical blanking and the total frame time
equations assume that the integration time (coarse
integration time plus fine integration time) is less than the
number of active lines plus the blanking lines:
WindowHeight ) VerticalBlanking
(eq. 1)
If this is not the case, the number of integration lines must
be used instead to determine the frame time, (see Table 5).
In this example, it is assumed that the coarse integration time
control is programmed with 2000 rows and the fine shutter
width total is zero.
For Master mode, if the integration time registers exceed
the total readout time, then the vertical blanking time is
internally extended automatically to adjust for the additional
integration time required. This extended value is not written
back to the frame_length_lines register. The
frame_length_lines register can be used to adjust
frametoframe readout time. This register does not affect
the exposure time but it may extend the readout time.
Table 5. FRAME TIME: LONG INTEGRATION TIME
Parameter Name Equation Timing at 74.25 MHz
F’ Total frame time (long
integration time)
Context A: (R0x3012 x (A + Q)) + R0x3014 + P1 + P2
Context B: (R0x3016 x (A + Q)) + V R0x3018 + P1 + P2
3,300,012 pixel clocks
= 44.44 ms
NOTE: The AR0130 uses column parallel analogdigital converters; thus short line timing is not possible. The minimum total line time is
1390 columns (horizontal width + horizontal blanking). The minimum horizontal blanking is 110.
Exposure
Total integration time is the result of
Coarse_Integration_Time and Fine_Integration_Time
registers, and depends also on whether manual or automatic
exposure is selected.
The actual total integration time, t
INT
is defined as:
t
INT
+ t
INTCoarse
* 410 * t
INTFine
(eq. 1)
= (number of lines of integration x line time) (410 pixel
clocks of conversion time overhead) (number of pixels of
integration x pixel time)
where:
Number of Lines of Integration (Auto Exposure
Control: Enabled)
When automatic exposure control (AEC) is enabled, the
number of lines of integration may vary from frame to
frame, with the limits controlled by R0x311E
(minimum auto exposure time) and R0x311C
(maximum auto exposure time).
Number of Lines of Integration (Auto Exposure
Control: Disabled)
If AEC is disabled, the number of lines of integration
equals the value in R0x3012 (context A) or R0x3016
(context B).
Number of Pixels of Integration
The number of fine shutter width pixels is independent
of AEC mode (enabled or disabled):
Context A: the number of pixels of integration
equals the value in R0x3014.
Context B: the number of pixels of integration
equals the value in R0x3018.
Typically, the value of the Coarse_Integration_Time
register is limited to the number of lines per frame (which
includes vertical blanking lines), such that the frame rate is
not affected by the integration time. For more information
on coarse and fine integration time settings limits, please
refer to the Register Reference document.

AR0130CSSC00SPBA0-DR1

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Image Sensors 1.2 MP 1/3 CIS
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