Application information USBDFxxW5
4/11
2.2 ESD protection
In addition to the requirements of termination and EMC compatibility, computing devices are
required to be tested for ESD susceptibility. This test is described in the IEC 61000-4-2 and
is already in place in Europe. This test requires that a device tolerates ESD events and
remain operational without user intervention.
The USBDFxxW5 is particularly optimized to perform ESD protection. ESD protection is
based on the use of device which clamps at :
This protection function is split in 2 stages. As shown in Figure 5., the ESD strikes are
clamped by the first stage S1 and then the remaining overvoltage is applied to the second
stage through the resistor R. Such a configuration makes the output voltage very low at the
V
out
level.
Figure 5. USBDFxxW5 ESD clamping behavior
Figure 3. Measurement configuration Figure 4. USBDFxxW5 attenuation
curve
50
RF IN
Vg
50
TG OUT
TEST BOARD
UD1
1 10 100 1000 3000
-30
-20
-10
0
F (MHz)
Insertion loss (dB)
V=V+ R.I
INPUT BR d pp
ESD Surge
Vinput
Voutput
Rload
Rg
R
S1
Rd
V
BR
V
BR
V
PP
Device
to be
protected
USBDFxxW5
Rd
S2
USBDFxxW5 Application information
5/11
To have a good approximation of the remaining voltages at both V
in
and V
out
stages, we give
the typical dynamical resistance value R
d
. Taking into account the following hypothesis:
R
t
> R
d
, R
g
> R and R
load
> R
d
, gives these formulas::
The results of the calculation done for V
PP
= 8 kV, R
g
= 330 W (IEC61000-4-2 standard),
V
BR
= 7 V (typ.) and R
d
= 1 (typ.) give:
V
input
= 31.2 V
V
output
= 7.95 V
This confirms the very low remaining voltage across the device to be protected. It is also
important to note that in this approximation the parasitic inductance effect was not taken into
account. This could be few tenths of volts during few ns at the V
in
side. This parasitic effect
is not present at the V
out
side due the low current involved after the resistance R.
The measurements results shown below show very clearly (Figure 7.) the high efficiency of
the ESD protection :
no influence of the parasitic inductances on Vout stage
output clamping voltage very close to V
BR
(positive strike) and -V
F
(negative strike)
Figure 6. Measurement board
V=
input
V=
output
R.V + R.V
gBR d g
R.V + R .V
t BR d inpu
t
R
g
R
t
TEST BOARD
ESD
SURGE
15 kV
Air
Discharge
Vin Vout
UD1
Application information USBDFxxW5
6/11
Figure 7. Remaining voltage at both stages S1 (V
input
) and S2 (V
output
) during ESD
surge
Note that the USBDFxxW5 is not only acting for positive ESD surges but also for negative
ones. Negative disturbances are clamped close to ground voltage as shown in Figure 7.b.
2.3 Latch-up phenomena
The early ageing and destruction of IC’s is often due to latch-up phenomena which is mainly
induced by dV/dt. Thanks to its structure, the USBDFxxW5 provides a high immunity to
latch-up phenomena by smoothing very fast edges.
2.4 Crosstalk behaviour
Figure 8. Crosstalk phenomena
The crosstalk phenomena is due to the coupling between 2 lines. The coupling factor ( β12
or β21 ) increases when the gap across lines decreases, this is the reason why we provide
crosstalk measurements for a monolithic device to guarantee negligeable crosstalk between
the lines. In the example above, the expected signal on load R
L2
is α
2
V
G2
, in fact the real
voltage at this point has got an extra value β21V
G1
. This part of the V
G1
signal represents
the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to
be taken into account when the drivers impose fast digital data or high frequency analog
signals in the disturbing line. The perturbed line will be more affected if it works with low
voltage signal or high load impedance (few k).
A. Positive surge B. Negative surge
Line 1
Line 2
V
G1
V
G2
R
G1
R
G2
DRIVERS
R
L1
R
L2
RECEIVERS
αβ
1 G1 1 2 G2
V+ V
αβ
2 G2 2 1 G1
V+ V

USBDF02W5

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
TVS Diodes / ESD Suppressors EMI Filter/Line Term
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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