W320-04H Datasheet W320-04HT, CYW320OXC-4T, CYW320OXC-4 | P1-P3

200 MHz Spread Spectrum Clock Synthesizer/Driver

with Differential CPU Outputs

W320-04

.......................Document #: 38-07010 Rev. *C Page 1 of 16

400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com

Features

• Compliant with Intel

CK-Titan clock synthesizer/driver

specifications

• Multiple output clocks at different frequencies

— Three pairs of differential CPU outputs, up to

200 MHz

— Ten synchronous PCI clocks, three free-running

— Six 3V66 clocks

— Two 48 MHz clocks

— One reference clock at 14.318 MHz

— One VCH clock

• Spread Spectrum clocking (down spread)

• Power-down features (PCI_STOP#, CPU_STOP#

PWR_DWN#)

• Three Select inputs (Mode select and IC Frequency

Select)

• OE and Test Mode support

• 56-pin SSOP package and 56-pin TSSOP package

Benefits

• Supports next-generation Pentium

processors using

differential clock drivers

• Motherboard clock generator

— Supports multiple CPUs and a chipset

— Support for PCI slots and chipset

— Supports AGP, DRCG reference, and Hub Link

— Supports USB host controller and graphic controller

— Supports ISA slots and I/O chip

• Enables reduction of electromagnetic interference

(EMI) and overall system cost

• Enables ACPI-compliant designs

• Supports up to four CPU clock frequencies

• Enables ATE and “bed of nails” testing

• Widely available standard package enables lower cost

Logic Block Diagram

SSOP and TSSOP

Top View

VDD_REF

XTAL_IN

XTAL_OUT

GND_REF

PCI0

PCI5

66BUFF2/3V66_4

GND_3V66

PCI_STOP#

GND_CPU

CPU_STOP#

PCI_F2

GND_PCI

GND_3V66

VDD_CORE

VDD_ 48 MHz

MULT0#

VDD_CPU

REF

PCI_F0

PCI_F1

VDD_PCI

GND_PCI

PCI1

PCI2

PCI3

VDD_PCI

PCI4

PCI6

VDD_3V66

66BUFF0/3V66_2

66BUFF1/3V66_3

66IN/3V66_5

PWR_DWN#

3V66_0

VDD_3V66

3V66_1/VCH

GND_ 48 MHz

DOT

USB

GND_IREF

IREF

CPU#2

CPU2

VDD_CPU

CPU#1

CPU1

CPU#0

CPU0

GND_CORE

PWR_GD#

SCLK

SDATA

W320-04

VDD_REF

CPU0:2

CPU#0:2

PCI_F0:2

XTAL

PLL Ref Freq

REF

VDD_PCI

USB (48MHz)

VCH_CLK/ 3V66_1

OSC

VDD_CPU

CPU_STOP#

SCLK

PCI0:6

PCI_STOP#

Stop

Clock

Control

Stop

Clock

Control

PLL 1

SMBus

Logic

DOT (48MHz)

PWR_DWN#

S0:2

VDD_48MHz

SDATA

VDD_3V66

3V66_0

3V66_2:4/

Divider

Network

3V66_5/ 66IN

PWR

PLL 2

PWR

66BUFF0:2

Gate

PWR_GD#

Pin Configurations

W320-04

.......................Document #: 38-07010 Rev. *C Page 2 of 16

Pin Summary

Name Pins Description

REF 56 3.3V 14.318-MHz clock output.

XTAL_IN 2 14.318-MHz crystal input.

XTAL_OUT 3 14.318-MHz crystal input.

CPU, CPU# [0:2] 44, 45, 48, 49, 51, 52 Differential CPU clock outputs.

3V66_0 33 3.3V 66-MHz clock output.

3V66_1/VCH 35 3.3V selectable through SMBus to be 66 MHz or 48 MHz.

66IN/3V66_5 24 66-MHz input to buffered 66BUFF and PCI or 66-MHz clock from

internal VCO.

66BUFF [2:0] /3V66 [4:2] 21, 22, 23 66-MHz buffered outputs from 66Input or 66-MHz clocks from internal

VCO.

PCI_F [0:2] 5, 6, 7, 33-MHz clocks divided down from 66Input or divided down from 3V66.

PCI [0:6] 10, 11, 12, 13, 16, 17, 18 PCI clock outputs divided down from 66Input or divided down from

3V66.

USB 39 Fixed 48-MHz clock output.

DOT 38 Fixed 48-MHz clock output.

S2 40 Special 3.3V 3-level input for Mode selection.

S1, S0 54, 55 3.3V LVTTL inputs for CPU frequency selection.

IREF 42 A precision resistor is attached to this pin, which is connected to the

internal current reference.

MULT0 43 3.3V LVTTL input for selecting the current multiplier for the CPU

outputs.

PWR_DWN# 25 3.3V LVTTL input for Power_Down# (active LOW).

PCI_STOP# 34 3.3V LVTTL input for PCI_STOP# (active LOW).

CPU_STOP# 53 3.3V LVTTL input for CPU_STOP# (active LOW).

PWRGD# 28 3.3V LVTTL input is a level sensitive strobe used to determine when

S[2:0] and MULTI0 inputs are valid and OK to be sampled (Active

LOW). Once PWRGD# is sampled LOW, the status of this output will

be ignored.

SDATA 29 SMBus compatible SDATA.

SCLK 30 SMBus compatible SCLK.

VDD_REF, VDD_PCI,

VDD_3V66, VDD_CPU

1, 8, 14, 19, 32, 46, 50 3.3V power supply for outputs.

VDD_48 MHz 37 3.3V power supply for 48 MHz.

VDD_CORE 26 3.3V power supply for PLL.

GND_REF, GND_PCI,

GND_3V66, GND_IREF,

VDD_CPU

4, 9, 15, 20, 31, 36, 41, 47 Ground for outputs.

GND_CORE 27 Ground for PLL.

W320-04

.......................Document #: 38-07010 Rev. *C Page 3 of 16

Function Table

[1]

S2 S1 S0

CPU

(MHz)

3V66[0:1]

(MHz)

66BUFF[0:2]/

3V66[2:4]

(MHz)

66IN/3V66_5

(MHz)

PCI_F/PCI

(MHz) REF0(MHz)

USB/DOT

(MHz) Notes

1 0 0 66 MHz 66 MHz 66IN 66 MHz Input 66IN/2 14.318 MHz 48 MHz 2, 3, 4

1 0 1 100 MHz 66 MHz 66IN 66 MHz Input 66IN/2 14.318 MHz 48 MHz 2, 3, 4

1 1 0 200 MHz 66 MHz 66IN 66 MHz Input 66IN/2 14.318 MHz 48 MHz 2, 3, 4

1 1 1 133 MHz 66 MHz 66IN 66 MHz Input 66IN/2 14.318 MHz 48 MHz 2, 3, 4

0 0 0 66 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4

0 0 1 100 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4

0 1 0 200 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4

0 1 1 133 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4

Mid 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1, 5

Mid 0 1 TCLK/2 TCLK/4 TCLK/4 TCLK/4 TCLK/8 TCLK TCLK/2 5, 6, 7

Mid 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved –

Mid 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved –

Swing Select Functions

Mult0 Board Target Trace/Term Z Reference R, IREF

/(3*Rr) Output Current V

@ Z

050 Rr = 221 1%, IREF = 5.00 mA I

= 4*IREF 1.0V @ 50

150 Rr = 475 1%, IREF = 2.32 mA I

= 6*IREF 0.7V @ 50

Clock Driver Impedances

Impedance

Buffer Name V

Range Buffer Type Min.  Typ.  Max. 

CPU, CPU# Type X1 50

REF 3.135–3.465 Type 5 12 30 55

PCI, 3V66, 66BUFF 3.135–3.465 Type 5 12 30 55

USB 3.135–3.465 Type 3A 12 30 60

DOT 3.135–3.465 Type 3B 12 30 60

Clock Enable Configuration

PWR_DWN# CPU_STOP# PCI_STOP# CPU CPU# 3V66 66BUFF PCI_F PCI USB/DOT VCOS/ OSC

0 X X IREF*2 FLOAT LOW LOW LOW LOW LOW OFF

1 0 0 ON FLOAT ON ON ON OFF ON ON

1 0 1 ON LOW ON ON ON ON ON ON

1 1 0 ON ON ON ON ON OFF ON ON

111ONONONONONONONON

Note:

1. TCLK is a test clock driven in on the XTALIN input in test mode.

2. “Normal” mode of operation

3. Range of reference frequency allowed is min. = 14.316, nom. = 14.31818 MHz, max. = 14.32 MHz.

4. Frequency accuracy of 48 MHz must be +167PPM to match USB default.

5. Mid. is defined a Voltage level between 1.0V and 1.8V for three-level input functionality. Low is below 0.8V. High is above 2.0V.

6. Required for DC output impedance verification.

7. These modes are to use the SAME internal dividers as the CPU = 200 MHz mode. The only change is to slow down the internal VCO to allow under clock

margining.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

W320-04H

Mfr. #:

Buy W320-04H

Manufacturer:

Silicon Labs

Description:

IC CLK/DRVR CPUOUT 200MHZ 56SSOP

Lifecycle:

New from this manufacturer.

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W320-04H

W320-04H

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