IDT
®
Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV Q 08/27/13
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
4
Electrical Characteristics - PCIEX 0.7V Current Mode Differential Pair
T
A
= Tambient; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2
Ω
, R
P
=49.9
Ω
, I
REF
= 475
Ω
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Current Source Output
Impedance
Zo V
O
= V
x
3000
Ω
1
Voltage High VHigh 660 850 1,3
Voltage Low VLow -150 150 1,3
Max Voltage Vovs 1150 1,3
Min Voltage Vuds -300 1,3
Crossing Voltage (abs) Vcross(abs) 250 350 550 mV 1,3
Crossing Voltage (var) d-Vcross
Variation of crossing over all
edges
12 140 mV 1,3
Long Accuracy ppm see Tperiod min-max values 0 ppm 1,2
100.00MHz nominal 9.9970 10.0030 ns 2
100.00MHz spread 9.9970 10.0533 ns 2
Absolute min period Tabsmin 100.00MHz nominal/spread 9.8720 ns 1,2
Rise Time t
r
V
OL
= 0.175V, V
OH
= 0.525V 175 700 ps 1
Fall Time t
f
V
OH
= 0.525V V
OL
= 0.175V 175 700 ps 1
Rise Time Variation d-t
r
30 125 ps 1
Fall Time Variation d-t
f
30 125 ps 1
t
d
PLL Mode. 0 150 ps 1
t
db
Bypass mode 3.7 4.2 ns 1
Duty Cycle d
t3
Measurement from differential
wavefrom
45 55 % 1
Output-to-Output Skew t
sk3
V
T
= 50% 25 ps 1
t
jcyc-cyc
PLL mode. Measurement from
differential wavefrom
35 ps 1
t
jcyc-cycbyp
Additve Jitter in Bypass Mode 30 ps 1
1
Guaranteed by design, not 100% tested in production.
.
3
I
REF
= V
DD
/(3xR
R
). For R
R
= 475
Ω
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
Ω
.
2
The 9DB102 does not add a ppm error to the input clock
Input to Output Delay
Jitter, Cycle to cycle
mV
Measurement on single ended
signal using absolute value.
mV
Average period Tperiod
Statistical measurement on
single ended signal using