OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

9DB102BGLFT

P1-P3P4-P6P7-P9P10-P12P13-P13
ICS9DB102
IDT
®
Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV Q 08/27/13
Two Output Differential Buffer for PCIe Gen1 & Gen2
DATASHEET
1
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
SMBDAT
SMBCLK
CLK_INT
C
L
K
_
I
N
C
PLL_BW
IREF
PCIEX0
PCIEX1
CLKREQ1#
CLKREQ0#
Description
Output Features
The ICS9DB102 zero-delay buffer supports PCI Express
clocking requirements. The ICS9DB102 is driven by a differential
SRC output pair from an ICS CK410/CK505-compliant main
clock. It attenuates jitter on the input clock and has a selectable
PLL Band Width to maximize performance in systems with or
without Spread-Spectrum clocking.
• 2 - 0.7V current mode differential output pairs (HCSL)
Functional Block Diagram
Key Specifications
• Cycle-to-cycle jitter < 35ps
• Output-to-output skew < 25ps
Features/Benefits
• CLKREQ# pin for outputs 1 and 4/output enable for Express
Card applications
• PLL or bypass mode/PLL can dejitter incoming clock
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL’s
• Spread Spectrum Compatible/tracks spreading input clock
for low EMI
• SMBus Interface/unused outputs can be disabled
• Industrial temperature range available
IDT
®
Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV Q 08/27/13
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
2
Pin Configuration
20-pin SSOP & TSSOP
VDD GND
5,9,12,16 6,15
PCI Ex
p
ress Out
p
uts
96
SMBUS
20 19 IREF
20 19 Analog VDD & GND for PLL core
Description
Pin Number
Power Groups
Pin Description
PLL_BW 1 20 VDDA
CLK_INT 2 19 GNDA
C LK_ INC 3 18 IREF
vCL KREQ0 # 4 17 vC LKREQ1#
VDD 5 16 VDD
GND 6 15 GND
PCIEXT0 7 14 PCIEXT1
PCIEXC0 8 13 PCIEXC1
VDD 9 12 VDD
SMBDAT
10 11 SMBCLK
ICS9DB102
Note:
Pins preceeded by ' v ' have internal
120K ohm pull down resistors
PIN # PIN NA ME PIN TYPE DESCRIPTION
1PLL_BW IN
3.3V inp ut for selectin g PLL Band Width
0 = low, 1= hi
g
h
2 CLK_INT IN True In
p
ut for differential reference clock.
3 CLK_INC IN Complementary Input for differential reference clock.
4 v CL KR EQ0 # IN
Output enabl e for PCI Expres s output pai r 0.
0 = enabled, 1 =disabled
5 VDD PWR Power su
pp
l
y
, nominal 3.3V
6
GND PWR Ground
p
in.
7
PCIEXT0 OUT True clock of differential PCI_Ex
p
ress
p
air.
8 PCIEXC0 OUT Complementary clock of differential PCI_Express pair.
9 VDD PWR Power supply, nominal 3.3V
10 SMBD AT I/O D ata pin o f SM BU S c ircuitr y, 5V tol erant
11 SMBC LK IN Clock
in of SMBUS circuitr
, 5V tolerant
12 VDD PWR Power su
pp
l
y
, nominal 3.3V
13 PC IEXC1 OU T C om
p
lementar
y
clock of differential PCI_Ex
p
ress
p
air.
14 PCIEXT1 OUT True clock of differential PCI_Express pair.
15 GND PWR Ground pin.
16 VDD PWR Power supply, nominal 3.3V
17 v CLKR EQ1# IN
Output enabl e for PCI Expres s output pai r 1.
0 = enabled, 1 =disabled
18 IREF OU T
This pin establi shes the r efe rence for the differ ential curr ent-m ode
output pairs. It requires a fixed precision resistor to ground. 475ohm is
the standard value for 100ohm differential impedance. Other
im
p
edanc es re
q
uire different values. See data sheet.
19 GNDA PWR Ground pin for the PLL core.
20 VDDA PWR 3.3V power for the PLL core.
Pins preceeded by ' v ' have internal 120K ohm pull down resistors
Note:
IDT
®
Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV Q 08/27/13
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
3
Absolute Max
Symbol Parameter Min Max Units
VDDA 3.3V Core Supply Voltage V
DD
+ 0.5V V
VDD 3.3V Output Supply Voltage GND - 0.5 V
DD
+ 0.5V V
Ts Storage Temperature -65 150
°
C
Tcase Case Temperature 115 °C
ESD prot
Input ESD protection
human body model
2000 V
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= Tambient; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Tambcom Commercial range 0 70 °C 1
Tambind Industrial range -40 85 °C 1
Input High Voltage V
IH
3.3 V +/-5% 2 V
DD
+ 0.3 V 1
Input Low Voltage V
IL
3.3 V +/-5% V
SS
- 0.3 0.8 V 1
Input High Current I
IH
V
IN
= V
DD
-5 5 uA 1
I
IL1
V
IN
= 0 V; Inputs with no pull-
up resistors
-5 uA 1
I
IL2
V
IN
= 0 V; Inputs with pull-up
resistors
-200 uA 1
Full Active, C
L
= Full load;
75
100 mA 1
all differential pairs tri-stated
27
50 mA 1
Input Frequency
3
F
i
V
DD
= 3.3 V 99 100 101 MHz 1
Pin Inductance
1
L
p
in
7nH1
C
IN
Logic Inputs 5 pF 1
C
OUT
Output pin capacitance 4.5 pF 1
Clk Stabilization
1,2
T
STAB
From V
DD
Power-Up to 1st
clock
1.8 ms 1
Modulation Frequency Triangular Modulation 30 33 kHz 1
Spread Spectrum Modulation
Frequency
f
MOD
Lexmark Modulation 25 45 KHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE#
deassertion
1 3 cycles 1,2
PLL Bandwidth when
PLL_BW=0
400 500 1000 KHz 1
PLL Bandwidth when
PLL_BW=1
22.53MHz1
SMBus Voltage V
DD
2.7 5.5 V 1
Low-level Output Voltage V
OLSMBUS
@ I
PULLUP
0.4 V 1
Current sinking at V
OL
= 0.4 V I
PULLUP
SMBus SDATA pin 4 mA 1
SCLK/SDATA
Clock/Data Rise Time
T
RI2C
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA
Clock/Data Fall Time
T
FI 2C
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Time from deassertion until outputs are >200mV
Tambient
PLL Bandwidth BW
Input Low Current
Input Capacitance
1
Operating Supply Current I
DD3.3OP
P1-P3P4-P6P7-P9P10-P12P13-P13

9DB102BGLFT

Mfr. #:
Buy 9DB102BGLFT
Manufacturer:
IDT
Description:
Clock Buffer 2 OUTPUT PCIE GEN2 BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet