IS64WV3216BLL-15CTLA3-TR

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7
Rev. B
07/22/09
IS64WV3216BLL
IS61WV3216BLL
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(OverOperatingRange)
-12 ns -15 ns
Symbol Parameter Min. Max. Min. Max. Unit
tr c ReadCycleTime 12 — 15 — ns
tA A AddressAccessTime — 12 — 15 ns
to H A OutputHoldTime 3 — 3 — ns
tA c e CEAccessTime — 12 — 15 ns
td o e OEAccessTime — 6 — 7 ns
tH z o e
(2)
OEtoHigh-ZOutput — 6 0 6 ns
tL z o e
(2)
OEtoLow-ZOutput 0 — 0 — ns
tH z c e
(2
CEtoHigh-ZOutput 0 6 0 6 ns
tL z c e
(2)
CEtoLow-ZOutput 3 — 3 — ns
tb A LB, UBAccessTime — 6 — 7 ns
tH z b LB, UBtoHigh-ZOutput 0 6 0 6 ns
tL z b LB, UBtoLow-ZOutput 0 — 0 — ns
Notes:
1. Testconditionsassumesignaltransitiontimesof1.5nsorless,timingreferencelevelsof1.25V,inputpulselevelsof0Vto
V
d d VandoutputloadingspeciedinFigure1a.
2. TestedwiththeloadinFigure1b.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
3. Not100%tested.
8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
07/22/09
IS64WV3216BLL
IS61WV3216BLL
READ CYCLE NO. 2
(1,3)
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (CS = OE=VI L, UB or LB = VI L)
Notes:
1. WEisHIGHforaReadCycle.
2. Thedeviceiscontinuouslyselected.OE, CE, UB, or LB = V
I L .
3. AddressisvalidpriortoorcoincidentwithCELOWtransition.
DATA VALID
PREVIOUS DATA VALID
tAA
tOHA
tOHA
tRC
DOUT
ADDRESS
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9
Rev. B
07/22/09
IS64WV3216BLL
IS61WV3216BLL
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(OverOperatingRange)
-12 ns -15 ns
Symbol Parameter Min. Max. Min. Max. Unit
tw c WriteCycleTime 12 — 15 — ns
ts c e CEtoWriteEnd 9 — 10 — ns
tA w AddressSetupTime 9 — 10 — ns
to Write End
tH A AddressHoldfromWriteEnd 0 — 0 — ns
ts A AddressSetupTime 0 — 0 — ns
tP w b LB, UBValidtoEndofWrite 9 — 10 — ns
tP w e 1 WEPulseWidth(OE=HIGH) 9 — 10 — ns
tP w e 2 WEPulseWidth(OE=LOW) 11 — 12 — ns
ts d DataSetuptoWriteEnd 9 — 9 — ns
tH d DataHoldfromWriteEnd 0 — 0 — ns
tH z w e
(3)
WELOWtoHigh-ZOutput — 6 — 7 ns
tL z w e
(3)
WEHIGHtoLow-ZOutput 3 — 3 — ns
Notes:
1. TestconditionsforIS61WV3216BLLassumesignaltransitiontimesof1.5nsorless,timingreferencelevelsof1.25V,inputpulse
levelsof0VtoV
d d VandoutputloadingspeciedinFigure1a.
2. TestedwiththeloadinFigure1b.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
3. TheinternalwritetimeisdenedbytheoverlapofCELOWandUB or LB, and WELOW.Allsignalsmustbeinvalidstatesto
initiateaWrite,butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtothe
rising or falling edge of the signal that terminates the write.

IS64WV3216BLL-15CTLA3-TR

Mfr. #:
Manufacturer:
ISSI
Description:
SRAM 512Kb (32Kx16) Async SRAM
Lifecycle:
New from this manufacturer.
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