Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. B
07/22/09
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
IS64WV3216BLL
IS61WV3216BLL
FUNCTIONAL BLOCK DIAGRAM
32K x 16 HIGH-SPEED CMOS STATIC RAM
JULY 2009
FEATURES
• High-speedaccesstime:
12ns:3.3V+ 10%
15ns:2.5V-3.6V
• CMOSlowpoweroperation:
50 mW (typical) operating
25 µW (typical) standby
• TTLcompatibleinterfacelevels
• Fullystaticoperation:noclockorrefresh
required
• Threestateoutputs
• Datacontrolforupperandlowerbytes
• AutomotiveTemperatureAvailable
• Lead-freeavailable
DESCRIPTION
TheISSIIS61/64WV3216BLLisahigh-speed,524,288-bit
static RAM organized as 32,768 words by 16 bits. It
is fabricated using ISSI's high-performance CMOS
technology.Thishighlyreliableprocesscoupledwithin-
novative circuit design techniques, yields access times as
fast as 12ns (3.3V+ 10%)and15ns(2.5V-3.6V)withlow
power consumption.
When CE is HIGH (deselected), the device assumes
a standby mode at which the power dissipation can be
reduceddownwithCMOSinputlevels.
Easy memory expansion is provided by using Chip Enable
andOutputEnableinputs,CE and OE.TheactiveLOW
Write Enable (WE) controls both writing and reading of the
memory.AdatabyteallowsUpperByte(UB)andLower
Byte(LB) access.
The IS61/64WV3216BLL is packaged in the JEDEC
standard44-pinTSOP-II,and48-pinminiBGA(6mmx
8mm).
A0-A14
CE
OE
WE
32Kx16
MEMORYARRAY
DECODER
COLUMNI/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
LowerByte
I/O8-I/O15
UpperByte
UB
LB