LTC1669
10
1669fa
APPLICATIONS INFORMATION
Slave Address (SOT-23 Package)
The slave address for the SOT-23 package has been
factory programmed to be “0100 000” (LTC
1669
) and
“0100 001” (LTC
1669
-1). If another address is required,
please consult the factory.
Command Byte
76543210
XXXXXBGSDSY
SY 1
0
Allows update on Acknowledge of SYNC Address only
Update on Stop condition only (Power-On Default)
SD 1
0
Puts the device in power-down mode
Puts the device in standard operating mode
(Power-On Default)
BG 1
0
Selects the internal bandgap reference
Selects the supply as the reference (Power-On Default)
X X Don’t Care
The stop condition normally initiates the update of the
DAC’s output latches. Simultaneous update of more than
one DAC or other devices on the bus can be achieved by
reissuing new start bit, address, command and data bytes
before issuing a fi nal stop condition (which will update
all the devices). An alternate way to achieve simultaneous
LTC1669 updates is to override the stop condition update
by setting the “SY” bit of the command byte. Setting this
bit sets the device to update the DAC output latches only
at the reception of a SYNC address quick command. The
actual update occurs on the rising edge of SCL during the
Acknowledge. In this way, all devices can update on the
reception of the SYNC address quick command instead
of the STOP condition.
A Shutdown (SD) bit = HIGH will put the device in a low
power state but retain all data latch information. Shutdown
will occur at the reception of a STOP condition. This way
shutdown could be synchronized to other devices. The
output impedance of the DAC will go to a high impedance
state (≈500kΩ to GND).
The Bandgap (BG) bit when set to “0” selects the DAC
supply voltage as its voltage reference. The full-scale
output of the DAC with this setting is equal to the supply
voltage. When the BG bit is set to “1,” the internal bandgap
reference (≈1.25V) is selected as the DAC’s reference. The
full-scale output voltage for this setting is 2.5V.
Data Bytes
Least Signifi cant Data Byte
76543210
D7 D6 D5 D4 D3 D2 D1 D0
Most Signifi cant Data Byte
76543210
XXXXXXD9D8
X = Don’t care
Send Byte Protocol
The Send Byte protocol used on the LTC1669 is actually a
subset of the Write Word protocol described previously.
The Send Byte protocol can only be used to send the
command byte information to the LTC1669.
Command Byte ASlave Address AWr PS
811711
1669 TA04
1
S = Start Condition, Wr = Write Bit, A = Acknowledge, P = Stop Condition
The Send Byte protocol is also used whenever the Write
Word protocol is interrupted for any reason. Reception of
a START or STOP condition after the Acknowledge of the
command byte, but before the Acknowledge of the last
data byte, will cause both data bytes to be ignored and
the command byte to be accepted.
Reception of a START or STOP condition before the Ac-
knowledge of the command byte will cause the interrupted
command byte to be ignored.
LTC1669
11
1669fa
APPLICATIONS INFORMATION
SYNC Address/Quick Command
In addition to the slave address, the LTC1669 has an address
that can be shared by other devices so that they may be
updated synchronously. The address is called to the SYNC
address and uses the quick command protocol.
The SYNC Address is 1111 110
Ack StopStart 1111 110 SY/CLR
1171
1669 TA05
1
SYNC Address
SY/CLR 1
0
Update output latches on rising edge of SCL during
Acknowledge of SYNC Address
Clear all internal latches on rising edge of SCL during
Acknowledge of SYNC Address
The SY/CLR bit set high only has meaning when the “SY”
bit of the command byte was previously set HIGH. On
the otherhand, the SY/CLR bit set LOW will always clear
the part, independent of the state of the “SY” bit in the
command byte.
Voltage Output
The output amplifi er contained in the LTC1669 can source
or sink up to 5mA. The output stage swings to within a
few millivolts of either supply rail when unloaded and
has an equivalent output resistance of 85Ω when driving
a load to the rails. The output amplifi er is stable driving
capacitive loads up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance greater
than 1000pF. For example, a 0.1μF load can be driven
by the LTC1669 if a 110Ω series resistance is used. The
phase margin of the resulting circuit is 45° and increases
monotonically from this point if larger values of resistance,
capacitance or both are substituted for the values given.
Rail-to-Rail Output Considerations
As in any rail-to-rail device, the output is limited to volt-
ages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.
Similarly, limiting can occur near full scale when V
CC
is
used as the reference. If V
REF
= V
CC
and the DAC full-scale
error (FSE) is positive, the output for the highest codes
limits at V
CC
as shown in Figure 1c. No full-scale limiting
can occur if the internal reference is used.
Offset and linearity are defi ned and tested over the region
of the DAC transfer function where no output limiting can
occur.
Internal Reference
In applications where a predictable output is required
that is independent of supply voltage, the LTC1669 has a
user-selectable internal reference. Selecting the internal
reference will set the full-scale output voltage to 2.5V. This
can be useful in applications where the supply voltage is
poorly regulated.
Using the LT
®
1460 Micropower Series Reference as a
Power Supply for the LTC1669
In applications where the advantages of using the internal
reference are required but the full-scale range needs to
be greater than 2.5V, an external series reference can be
used. The LT1460 is ideal for use as a power supply for
the LTC1669 and can provide 3V, 3.3V and 5V full-scale
output voltage ranges. The LT1460 provides accuracy, noise
immunity and extended supply range to the LTC1669 when
the LTC1669 is operated ratiometric to V
CC
. Since both
parts are available in SOT-23 packages, the PC board space
for this application is extremely small. See Figure 2.
LTC1669
12
1669fa
APPLICATIONS INFORMATION
Figure 1. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V
REF
= V
CC
1669 F01
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
5120 1023
INPUT CODE
OUTPUT
VOLTAGE
(a)
V
REF
= V
CC
V
REF
= V
CC
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE

LTC1669IMS8#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Single I2C 10-Bit DAC in MSOP
Lifecycle:
New from this manufacturer.
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