6.42
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
7
IDT70P264/254/244L Datasheet
R1
R2
3
0pF
3
.
0
/
2
.
5
1
.
8
7148 drw 03
Figure 1A. AC Output Test Load
(5pF for t
LZ, tHZ, tWZ, tOW)
3.0V/2.5V 1.8V
R1 1022 13500
R2 729 10800
7148 tbl 10_5
Timing of Power-Up Power-Down
7148 drw 04
t
PU
I
CC
I
SB
t
PD
CE
50%
50
%
,
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V/GND to 2.5V/GND to 1.8V
3ns Max.
1.5V/1.25V/0.9V
1.5V/1.25V/0.9V
Figure 1A
7148 tbl 10
R3 = 1k
30pF
3
.
3
7148 drw 03a
Figure 1B. AC Output Test Load for Interrupt
6.42
IDT70P264/254/244L Datasheet
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
8
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(2)
NOTES:
1. This parameter is guaranteed by device characterization, but is not production tested.
2. The specification for t
DH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual t
DH will always be smaller than the actual tOW.
3. At any given temperature and voltage condition, t
HZ is less than tLZ for any given device.
Symbol
70P264/254/244
Ind'l Only
UnitParameter
40ns 55ns
Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 40
____
55
____
ns
t
AA
Address Access Time
____
40
____
55 ns
t
ACE
Chip Enable Access Time
____
40
____
55 ns
t
ABE
Byte Enable Access Time
____
40
____
55 ns
t
AOE
Output Enable Access Time
____
25
____
30 ns
t
OH
Output Hold from Address Change 5
____
5
____
ns
t
LZ
Output Low-Z Time
(1,3)
5
____
5
____
ns
t
HZ
Output High-Z Time
(1,3)
____
10
____
25 ns
t
PU
Chip Enable to Power Up Time
(1)
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(1)
____
40
____
55 ns
7148 tbl 11
6.42
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
9
IDT70P264/254/244L Datasheet
t
RC
R/W
CE
ADDRESS
t
AA
OE
UB, LB
7148 drw 05
t
ACE
t
AOE
t
ABE
(1)
t
LZ
t
OH
(2)
t
HZ
DATA
OUT
VALID DATA
,
Waveform of Read Cycles
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.

70P264L40BYGI8

Mfr. #:
Manufacturer:
Description:
IC SRAM 256K PARALLEL 81CABGA
Lifecycle:
New from this manufacturer.
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