6.42
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
13
IDT70P264/254/244L Datasheet
Truth Table II — Interrupt Flag
(1)
NOTES:
1. A
13X is a NC for IDT70P254. A13X and A12X are NC for IDT70P244. Interrupt Addresses are 1FFF and 1FFE for IDT70P254 and FFF and FFE for IDT70P244.
Left Port Right Port
FunctionR/W
L
CE
L
OE
L
A
13L
-A
0L
(1)
INT
L
R/W
R
CE
R
OE
R
A
13R
-A
0R
(1)
INT
R
LLX3FFFXXXX X LSet Right INT
R
Flag
X X X X X X L L 3FFF H Reset Right INT
R
Flag
X X X X L L L X 3FFE X Set Left INT
L
Flag
X L L 3FFE H X X X X X Reset Left INT
L
Flag
7148 tbl 14
Functional Description
The IDT70P264/254/244 provides two ports with separate control,
address and I/O pins that permit independent access to any location in
memory. The IDT70P264/254/244 has an automatic power down feature
controlled by CE. The CE controls on-chip power down circuitry that
permits the respective port to go into a standby mode when not selected
(CE HIGH). When a port is enabled, access to the entire memory array
is permitted.
Power Supply
Each port can operate on independent I/O voltages. This is deter-
mined by what is connected to the V
DDIOL and VDD pins. The supported
I/O standards are 1.8V/2.5V LVCMOS and 3.0V LVTTL.
The IDT70P264/254/244 includes power supply isolation functional-
ity which aids system power management. V
DD and VDDIOL can be
independently powered up/down which allows the left port or the right port
and core to be powered down when not in use. If VDDIOL is powered down,
but V
DD remains powered up all inputs to the core from the left port will be
forced to deasserted states at full swing DC values to minimize leakage
current and active power consumption. If VDD is powered down but VDDIOL
remain powered up, all outputs for the left port will remain in the state they
were in prior to power down.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 3FFE
(HEX) (1FFE for IDT70P254, FFE for IDT70P244), where a write is
defined as the CE=R/W=VIL per Truth Table II. The left port clears the
interrupt by accessing address location 3FFE (1FFE for IDT70P254, FFE
for IDT70P244) when CER = OER = VIL, R/W is a "don't care". Likewise,
the right port interrupt flag (INT
R) is asserted when the left port writes to
memory location 3FFF (HEX) (1FFF for IDT70P254, FFF for IDT70P244)
and to clear the interrupt flag (INTR), the right port must read the memory
location 3FFF. The message (16 bits) at 3FFE or 3FFF is user-defined,
since it is an addressable SRAM location. If the interrupt function is not used,
address locations 3FFE and 3FFF are not used as mail boxes, but as part
of the random access memory. Refer to Truth Table II for the interrupt
operation.
The interrupt outputs of the IDT70P264/254/244 should be connected
to an interrupt power supply (VDDINT
X) through an external pull-up
resistor. As long as VDDINT
R > VDD and VDDINTL > VDDQL, there will
be no current flowing between VDDINTx and VDD/VDDQ
L.
