P3041 Features
P3041 QorIQ Communications Processor Product Brief, Rev. 0
Freescale Semiconductor 7
— CoreNet fabric supporting coherent and non-coherent transactions with prioritization and
bandwidth allocation amongst CoreNet end-points
— Queue manager fabric supporting packet-level queue management and quality of service
scheduling
• One 64-bit DDR3/3L SDRAM memory controller with ECC and chip-select interleaving support
• Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following
functions:
— Frame management for packet parsing, classification, and distribution
— Queue management for scheduling, packet sequencing, and congestion management
— Hardware buffer management for buffer allocation and de-allocation
— Encryption/decryption (SEC 4.2)
— RegEx pattern matching (PME 2.1)
— RapidIO™ messaging manager (RMan)
• Ethernet interfaces
— One 10 Gbps Ethernet (XAUI) controller
— Five 1 Gbps or four 2.5 Gbps Ethernet controllers
• High speed peripheral interfaces
— Four PCI Express 2.0 controllers/ports running at up to 5 GHz
— Two Serial RapidIO® controllers/ports (version 1.3 with features of 2.1) running at up to
5 GHz
– RapidIO message manager (RMan) with Type 5–6 and Type 8–11 support
— Dual SATA 2.0 interfaces
• Additional peripheral interfaces
— Two USB 2.0 controllers with integrated PHY
— SD/MMC controller (eSDHC)
— Enhanced SPI controller
— Four I
2
C controllers
— Dual DUARTs
— Dual SATA supporting 1.5 and 3.0 Gb/s operation
• 18 SerDes lanes to 5 GHz
• Enhanced local bus controller (eLBC)
• Multicore programmable interrupt controller (MPIC)
• Two 4-channel DMA engines
3.3 P3041 Benefits
The P3041’s e500mc cores can be combined as a fully-symmetric, multi-processing, system-on-a-chip, or
they can be operated with varying degrees of independence to perform asymmetric multi-processing. Full
processor independence, including the ability to independently boot and reset each e500mc core, is a