OM13489 16-bit GPIO User Manual
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© NXP B.V. 2014. All rights reserved.
Rev. 2.0 — 09 January 2014
4.5 PCA9673, PCAL9539A, PCA9539A, PCA9539R, PCA9539
The PCA9673 and PCA9539 series implement two address pins, RST and INT . This
configuration ignores the power supply setup, but normally, only JP4 with a jumper between
pins 2 & 3 need be applied to power the device at 3.3V.
To configure the function pins, apply jumpers between pins 2 & 3 on JP9 and JP11 to
configure device pin 3 as
RST and device pin 1 as INT . Apply a jumper between pins 1 &
2 on JP10 to configure device pin 2 as an address.
Then, apply jumpers to JP1 and JP7 to configure the desired I
2
C address. Logic high or logic
low are labeled on the board. Leave JP8 open. The labels are incorrect for JP7 and JP8.
Using the labels, a 0 is actually a 1 and a labeled 1 is actually a 0. The schematic is correct
and note the square solder pad is pin 1.
Fig 7. Jumper Configuration for PCA9673, PCAL9539A, PCA9539A, PCA9539R,
PCA9539
4.6 PCAL6416A, PCA6416A
The PCA(L)6416A devices are level translating, Agile I/0 Expanders with two power supplies,
one address pin,
RST and INT . The two power supplies may operate at different voltages
to translate from the I
2
C-bus voltage domain to a higher or lower I/O voltage. CN3 and JP4
may be set to the same or different voltages, or left open and external voltage sources
connected to TP1 and TP2. See the datasheet for more details on voltage level translation.
Note that the 10K pull up resistors SDA and SCL, R5 and R6, are connected to VDDP which
may cause incorrect current readings if two different supplies are used.
To configure the function pins, apply jumpers between pins 2 & 3 on JP9, J10 and JP11 to
configure device pin 2 as a power supply, device pin 3 as
RST and device pin 1 as INT .
Then, apply a jumper to JP1 to configure the desired I
2
C address. Logic high or logic low are
labeled on the board. Leave JP7 and JP8 open.
