AD10242
–12–
USING THE FLEXIBLE INPUT
The AD10242 has been designed with the user’s ease of opera-
tion in mind. Multiple input configurations have been included on
board to allow the user a choice of input signal levels and input
impedance. While the standard inputs are ± 0.5 V, ± 1.0 V, and
± 2.0 V, the user can select the input impedance of the AD10242
on any input by using the other inputs as alternate locations for
GND or an external resistor. The following chart summarizes the
impedance options available at each input location:
A
IN
1 = 100 when A
IN
2 and A
IN
3 are open.
A
IN
1 = 75 when A
IN
3 is shorted to GND.
A
IN
1 = 50 when A
IN
2 is shorted to GND.
A
IN
2 = 200 when A
IN
3 is open.
A
IN
2 = 100 when A
IN
3 is shorted to GND.
A
IN
2 = 75 when A
IN
2 to A
IN
3 has an external resistor of
A
IN
2 = 300 , with A
IN
3 shorted to GND.
A
IN
2 = 50 when A
IN
2 to A
IN
3 has an external resistor of A
IN
2
= 100 , with A
IN
3 shorted to GND.
A
IN
3 = 400 .
A
IN
3 = 100 when A
IN
3 has an external resistor of 133 to GND.
A
IN
3 = 75 when A
IN
3 has an external resistor of 92 to GND.
A
IN
3 = 50 when A
IN
3 has an external resistor of 57 to GND.
While the analog inputs of the AD10242 are designed for
dc- coupled
bipolar inputs, the AD10242 has the ability to
use unipolar inputs in a user selectable mode through the addi-
tion of an external resistor. This allows for 1 V, 2 V, and 4 V
full-scale unipolar signals to be applied to the various inputs
(A
IN
1, A
IN
2, and A
IN
3, respectively). Placing a 2.43 k resis-
tor (typical, offset calibration required) between UPOS and
UCOM shifts the reference voltage setpoint to allow a unipolar
positive voltage to be applied at the inputs of the device. To cali-
brate offset, apply a midscale dc voltage to the converter while
adjusting the unipolar resistor for a midscale output transition.
A
IN
2
UPOS
AD10242
2.43k
UCOM
A
IN
3
A
IN
1
Figure 13. Unipolar Positive
To operate with –1 V, –2 V, or –4 V full-scale unipolar signals,
place a 2.67 k resistor (typical, offset calibration required)
between UNEG and UCOM. This again shifts the reference volt-
age setpoint to allow a unipolar negative voltage to be applied at
the inputs of the device. To calibrate offset, apply a midscale dc
voltage to the converter while adjusting the unipolar resistor for
a midscale output transition.
A
IN
2
UNEG
AD10242
2.67k
UCOM
A
IN
3
A
IN
1
Figure 14. Unipolar Negative
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in any high speed, high resolution
system. Multilayer printed circuit boards (PCBs) are recom-
mended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:
1. The minimization of the loop area encompassed by a signal
and its return path.
2. The minimization of the impedance associated with ground
and power paths.
3. The inherent distributed capacitor formed by the power
plane, PCB insulation, and ground plane.
These characteristics result in both a reduction of electro-
magnetic interference (EMI) and an overall improvement in
performance.
It is important to design a layout that prevents noise from cou-
pling to the input signal. Digital signals should not be run in
parallel with input signal traces and should be routed away from
the input circuitry. The AD10242 does not distinguish between
analog and digital ground pins as the AD10242 should always
be treated like an analog component. All ground pins should be
connected together directly under the AD10242. The PCB
should have a ground plane covering all unused portions of the
component side of the board to provide a low impedance path
and manage the power and ground currents. The ground plane
should be removed from the area near the input pins to reduce
stray capacitance.
LAYOUT INFORMATION
The schematic of the evaluation board (Figure 15) represents a
typical implementation of the AD10242. The pinout of the
AD10242 is very straightforward and facilitates ease of use
and the implementation of high frequency/high resolution
design practices. It is recommended that high quality ceramic
chip capacitors be used to decouple each supply pin to ground
directly at the device. All capacitors except the one placed on
ENCODE can be standard high quality ceramic chip capacitors.
The capacitor used on the ENCODE pin must be a low induc-
tance chip capacitor as referenced previously.
REV. D
AD10242
–13–
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9618765 686766656463624321
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
26
21
27 4328 29 30 31 32 33 34 35 36 37 38 39 40 41 42
DUT
AD10242
D0A
D11B
A
IN
A3
A
IN
A2
A
IN
A1
A
IN
B3
A
IN
B2
A
IN
B1
GND
GND
GND
GND
GND
TP5
TP6
GND
GND
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
D10B
D9B
D8B
D7B
GND
–5.2V
+5VA
GND
GND
GND
GND
GND
GND
GND
TP2
TP3
TP4
GND
GND
ENCB
ENCB
+5VD
GND
ENCA
ENCA
+5VD
D9A
D10A
D11A
GND
GND
D0B
D1B
D2B
D3B
D4B
D5B
D6B
GND
GND
TP1
–5.2V
+5VA
(MSBB) D11B
D10B
D9B
D8B
D7B
GNDB
GNDB
GNDB
GNDB
UNIPOSB
UNINEGB
UNICOMB
GNDB
GNDB
ENCB
ENCB
+5VDB
D0A (LSBA)
GNDA
GNDA
GNDA
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
NCA
NCA
UNIPOSA
–5.2VAA
+5VAA
A
IN
A3
A
IN
A2
A
IN
A1
A
IN
B3
A
IN
B2
A
IN
B1
GNDB
GNDB
UNICOMA
UNINEGA
SHIELD
+5VAB
–5.2VAB
GNDA
GNDA
GNDA
GNDA
GNDB
ENCA
ENCA
+5VDA
D9A
D10A
D11A (MSBA)
NCB
NCB
D0B (LSBB)
D1B
D2B
D3B
D4B
D5B
D6B
GNDB
5
8
6
3
2
R7
49.9
R3
470
R5
470
VHIGH
PULSE A
IN
U3
AD8036Q
SMA
J11
SMA
J12
PULSE A
OUT
VLOW
5VA
5VA
C1
0.1F
14
U1
K1115
7
8
H2DM
J15
H2DM
J17
BUFLATA
SMA
JC
SMA
J1
SMA
JA
C14
0.1F
R10
470
R9
470
2
3
8
U5
AD9696KN
E5
5
7
12
12
A SECTION
T1
T1–1T
2
1
3
4
6
ENCAB
ENCA
1 : 1
GND
R1
100
V
CC
OUT
V
EE
51
SMA
J2
A
IN
A1
SMA
J3
A
IN
A2
SMA
J4
A
IN
A3
SMA
J5
A
IN
B1
SMA
J6
A
IN
B2
SMA
J7
A
IN
B3
U4
C17
0.1F
U3
C18
0.1F
DUT
C9
0.1F
C23
10F
U5
C12
0.1F
U6
C3
0.1F
DUT
C8
0.1F
+5VD
U3
C15
0.1F
U4
C16
0.1F
C24
10F
U5
C13
0.1F
U6
C4
0.1F
DUT
C11
0.1F
–5.2V
DUT
C10
0.1F
DUT
C7
0.1F
C25
10F
DUT
C6
0.1F
+5V
VHIGH
U4
C22
0.1F
U3
C21
0.1F
VLOW
U3
C19
0.1F
U4
C20
0.1µF
+5VA
+5VA
E1
VHIGH
VHIGH
VLOW VLOW
GND
GND
E3
–5.2V
–5.2V
E2
B JACKS
TP2 TP2
TP1 TP1
TP3 TP3
TP4 TP4
TP5 TP5
TP7
ENCAB
TP6
TP6
TP8
ENCA
TP9
ENCBB
TP10
ENCB
TEST POINTS
+5VD
140
(MSB) D11B
239
D10B
338
D8B
536
D9B
437
D7B
635
D6B
734
D4B
932
D5B
833
10 31
11
30
D2B
13
28
D3B
12 29
D1B
(LSB) D0B
15 26
GND
17 24
GND
16 25
14
27
GND
18 23
GND
20 21
GND
19 22
H40DM
J10
BUFLATB
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
5VD
140
(MSB) D11A
239
D10A
338
D8A
536
D9A
437
D7A
635
D6A
734
D4A
932
D5A
833
10 31
BUFLATA
11
30
D2A
128
D3A
12 29
13
D1A
(LSB) D0A
15 26
GND
17 24
GND
16 25
14 27
GND
18 23
GND
20 21
GND
19 22
H40DM
J9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
E4
5VA
5VA
C2
0.1F
14
U2
K1115
7
8
H2DM
J16
H2DM
J18
BUFLATB
SMA
J8
SMA
JB
SMA
JD
C5
0.1F
R12
470
R11
470
2
3
8
U5
AD9696KN
E5
5
7
12
12
B SECTION
OUT
T2
T1–1T
2
1
3
4
6
ENCBB
ENCB
1 : 1
GND
R2
100
51
NOTES;
1) UNIPOLAR OPERATION
A SIDE + CONNECT 2.43k RES. FROM TP1 TO TP5.
A SIDE – CONNECT 2.67k RES. FROM TP5 TO TP6.
B SIDE + CONNECT 2.43k RES. FROM TP2 TO TP4.
B SIDE – CONNECT 2.67k RES. FROM TP4 TO TP3.
2) ABOVE UNIPOLAR RESISTOR VALUES ARE
NOMINAL AND MAY HAVE TO BE ADJUSTED
DEPENDING ON OFFSET OF DUT.
3) ENCODE SOURCES
A)FOR NORMAL OPERATION, A 40MHz TTL CLOCK
OSCILLATOR IS INSTALLED IN U1 AND U2. THERE
IS A 51 RESISTOR BETWEEN J15 AND J16.
J17 AND J18 ARE OPEN.
B)FOR EXTERNAL SQUARE WAVE ENCODE, INPUT
SIGNAL AT J1 AND J8, REMOVE U1, U2, JUMPERS
J15 AND J16. CONNECT JUMPERS J17 AND J18.
C)FOR EXTERNAL SINE WAVE ENCODE, INPUT
SIGNAL AT J1 AND J8, REMOVE U1, U2, R9, R11,
JUMPERS J15 AND J16.
CONNECT JUMPERS J17 AND J18.
4) POWER (5VD) FOR DIGITAL OUTPUTS OF THE
AD10242 IS SUPPLIED VIA PIN 1 OF EITHER J9 OR J10
(THE DIGITAL INTERFACES). TO POWER THE EVAL.
BOARD WITH ONE 5V SUPPLY, JUMPER A WIRE
FROM E1 TO E4 (CONNECTED AT FACTORY).
5
8
6
3
2
R8
49.9
R4
470
R6
470
VHIGH
PULSE B
IN
U4
AD8036Q
SMA
J13
SMA
J14
PULSE B
OUT
VLOW
V
CC
V
EE
Figure 15. Evaluation Board Schematic
REV. D
AD10242
–14–
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
connect directly to the receiving gate. Internal circuitry buffers
the outputs of the AD9042 ADC through a resistor network to
eliminate the need to externally isolate the device from the
receiving gate.
EVALUATION BOARD
The AD10242 evaluation board (see Figure 16) is designed to
provide optimal performance for evaluation of the AD10242
analog-to-digital converter. The board encompasses everything
needed to ensure the highest level of performance for evaluating
the AD10242.
Power to the analog supply pins is connected via banana jacks.
The analog supply powers the crystal oscillator, the associated
components and amplifiers, and the analog section of the
AD10242. The digital outputs of the AD10242 are powered via
Pin 1 of either J9 or J10 found on the digital interface con-
nector. To power the evaluation board with one 5 V supply, a
jumper wire is required from test point E1 to E4. Contact the
factory if additional layout or applications assistance is required.
Figure 16. Evaluation Board Mechanical Layout
REV. D

AD10242BZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC IC Dual 12-Bit 41MSPS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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