SiP32458, SiP32459
Vishay Siliconix
Document Number: 63999
S13-1423-Rev. B, 24-Jun-13
www.vishay.com
7
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: powerictechsupport@vishay.com
TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
TYPICAL WAVEFORMS
Figure 20 - Turn-Off Delay Time vs. Temperature
10.00
12.00
14.00
16.00
18.00
20.00
22.00
24.00
- 40 - 20 0 20 40 60 80 100
t
d(off)
- Turn-Off Delay Time (μs)
Temperature (°C)
V
IN
= 4.5 V
C
L
= 100 μF
R
L
= 5 Ω
Figure 21 - Turn-Off Delay Time vs. Temperature
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
- 40 - 20 0 20 40 60 80 100
t
d(off)
- Turn-Off Delay Time (ms)
Temperature (°C)
V
IN
= 4.5 V
C
L
= 100 μF
R
L
= 150 Ω
SiP32458
SiP32459
Figure 22 - Turn-On Time
(V
IN
= 4.5 V, R
L
= 5 , C
L
= 100 µF)
Figure 23 - Turn-Off Time
(V
IN
= 4.5 V, R
L
= 5 , C
L
= 100 µF)
Figure 24 - Turn-On Time
(V
IN
= 4.5 V, R
L
= 150 , C
L
= 100 µF)
Figure 25 - Turn-Off Time, SiP32458
(V
IN
= 4.5 V, R
L
= 150 , C
L
= 100 µF)
www.vishay.com
8
Document Number: 63999
S13-1423-Rev. B, 24-Jun-13
Vishay Siliconix
SiP32458, SiP32459
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: powerictechsupport@vishay.com
DETAILED DESCRIPTION
SiP32458 and SiP32459 are P-channel power MOSFET
designed as high side load switches. They incorporate a
negative charge pump at the gate to keep the gate to source
voltage high when turned on therefore keep the on
resistance low at lower input voltage range. SiP32458 and
SiP32459 are designed with slow slew rate to minimize the
inrush current during turn on. The SiP32458 has a reverse
blocking circuit to prevent the current from going back to the
input in case the output voltage is higher than the input
voltage. The SiP32459 has an output pulldown resistor to
discharge the output capacitance when the device is off.
APPLICATION INFORMATION
Input Capacitor
While a bypass capacitor on the input is not required,
a 4.7 µF or larger capacitor for C
IN
is recommended in almost
all applications. The bypass capacitor should be placed as
physically close as possible to the input pin to be effective in
minimizing transients on the input. Ceramic capacitors are
recommended over tantalum because of their ability to
withstand input current surges from low impedance sources
such as batteries in portable devices.
Output Capacitor
A 0.1 µF capacitor across V
OUT
and GND is recommended
to insure proper slew operation. There is inrush current
through the output MOSFET and the magnitude of the inrush
current depends on the output capacitor, the bigger the C
OUT
the higher the inrush current. There are no ESR or capacitor
type requirement.
Enable
The EN pin is compatible with CMOS logic voltage levels. It
requires at least 0.4 V or below to fully shut down the device
and 1 V or above to fully turn on the device. There is a
2.8 M resistor connected between EN pin and GND pin.
Protection Against Reverse Voltage Condition
The SiP32458 contains the reverse blocking circuit to keep
the output current from flowing back to the input in case the
output voltage is higher than the input voltage.
Thermal Considerations
These devices are designed to maintain a constant output
load current. Due to physical limitations of the layout and
assembly of the device the maximum switch current is 3 A as
stated in the Absolute Maximum Ratings table. However,
another limiting characteristic for the safe operating load
current is the thermal power dissipation of the package. To
obtain the highest power dissipation (and a thermal
resistance of 110 °C/W) the device should be connected to a
heat sink on the printed circuit board.
The maximum power dissipation in any application
is dependant on the maximum junction temperature,
T
J(max.)
= 125 °C, the junction-to-ambient thermal resistance,
J-A
= 110 °C/W, and the ambient temperature, T
A
, which
may be formulaically expressed as:
It then follows that, assuming an ambient temperature of
70 °C, the maximum power dissipation will be limited to about
500 mW.
So long as the load current is below the 3 A limit, the
maximum continuous switch current becomes a function two
things: the package power dissipation and the R
DS(ON)
at the
ambient temperature.
As an example let us calculate the worst case maximum load
current at T
A
= 70 °C. The worst case R
DS(ON)
at 25 °C is
36 m at V
IN
= 1.5 V. The R
DS(ON)
at 70 °C can be
extrapolated from this data using the following formula:
R
DS(ON)
(at 70 °C) = R
DS(ON)
(at 25 °C) x (1 + T
C
x T)
Where T
C
is 2820 ppm/°C. Continuing with the calculation
we have
R
DS(ON)
(at 70 °C) = 36 m x (1 + 0.00282 x (70 °C - 25 °C))
= 40.5 m
The maximum current limit is then determined by
which in this case is 3.5 A. Under the stated input voltage
condition, if the 3.5 A current limit is exceeded the internal die
temperature will rise and eventually, possibly damage the
device.
To avoid possible permanent damage to the device and keep
a reasonable design margin, it is recommended to operate
the device maximum up to 3 A only as listed in the Absolute
Maximum Ratings table.
Figure 26 - Turn-Off Time, SiP32459
(V
IN
= 4.5 V, R
L
= 150 , C
L
= 100 µF)
280
125
(max.)
(max.)
A
A
J
A
J
T
TT
P
-
=
-
=
-
θ
) (
(max.)
(max.)
ON DS
LOAD
R
P
I <
SiP32458, SiP32459
Vishay Siliconix
Document Number: 63999
S13-1423-Rev. B, 24-Jun-13
www.vishay.com
9
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: powerictechsupport@vishay.com
PACKAGE OUTLINE
WCSP: 6 Bumps (2 x 3, 0.5 mm Pitch, 250 µm Bump Height, 1 mm x 1.5 mm Die Size)
Notes (unless otherwise specified)
1. Laser mark on the silicon die back coated with an epoxy film.
2. Bumps are SAC396.
3. 0.050 max. co-planarity.
4. Laminate tape thickness is 0.022 mm.
5. Use millimeters as the primary measurement.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?63999
Dimension
MILLIMETERS
5
INCHES
Min. Nom. MAX. Min. Nom. MAX.
A 0.540 0.572 0.620 0.0212 0.0225 0.0244
A1 0.214 0.250 0.286 0.0084 0.0098 0.0113
b 0.279 0.310 0.372 0.0109 0.0122 0.0146
e 0.500 0.0197
s 0.230 0.250 0.270 0.0090 0.0098 0.0106
D 0.920 0.960 1.000 0.0362 0.0378 0.0394
E 1.420 1.460 1.500 0.0559 0.0575 0.0591
b
D
es
A
A1
s
E
e s
s
AB
Top View
e
e
ee
Index Bump A1
A1
A1
A2B2
B1
C1
C2
Bottom View
Side View
Note 3
Bump Note 2
RECOMMENDED
LAND PATTERN
W
Note 4

SIP32458EVB

Mfr. #:
Manufacturer:
Vishay / Siliconix
Description:
Power Management IC Development Tools Development Board For SiP32458 Series
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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