4 Typical Circuit VIPer100-E
10/29
4 Typical Circuit
Figure 3. Offline Power Supply With Auxiliary Supply Feedback
Figure 4. Offline Power Supply With Optocoupler Feedback
AC IN
+Vcc
GND
F1
BR1
D3
R9
C1
R7
C4
C2
TR2
R1
C3
D1
D2
C10
TR1
C9
C7
L2
R3
C6
C5
R2
U1
VIPer100
-
+
13V
OSC
COMP SOURCE
DRAI NVDD
FC00081
C11
FC00091
AC IN
F1
BR1
D3
R9
C1
R7
C4
C2
TR2
R1
C3
D1
D2
C10
TR1
C9C7
L2
+Vcc
GND
C8
C5
R2
U1
VIPer100
U2
R4
R5
ISO1
R6
R3
C6
-
+
13V
OSC
COMP SOURCE
DRAINVDD
C11
VIPer100-E 5 Operation Description
11/29
5 Operation Description
5.1 Current Mode Topology:
The current mode control method, like the one integrated in the VIPer100-E, uses two control
loops - an inner current control loop and an outer loop for voltage control. When the Power
MOSFET output transistor is on, the inductor current (primary side of the transformer) is
monitored with a SenseFET technique and converted into a voltage V
S
proportional to this
current. When V
S
reaches V
COMP
(the amplified output voltage error) the power switch is
switched off. Thus, the outer voltage control loop defines the level at which the inner loop
regulates peak current through the power switch and the primary winding of the transformer.
Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input
voltage feedforward characteristic of the current mode control. This results in improved line
regulation, instantaneous correction to line changes, and better stability for the voltage
regulation loop.
Current mode topology also ensures good limitation in case there is a short circuit. During the
first phase the output current increases slowly following the dynamic of the regulation loop.
Then it reaches the maximum limitation current internally set and finally stops because the
power supply on V
DD
is no longer correct. For specific applications the maximum peak current
internally set can be overridden by externally limiting the voltage excursion on the COMP pin.
An integrated blanking filter inhibits the PWM comparator output for a short time after the
integrated Power MOSFET is switched on. This function prevents anomalous or premature
termination of the switching pulse in case there are current spikes caused by primary side
capacitance or secondary side rectifier reverse recovery time.
5.2 Stand-by Mode
Stand-by operation in nearly open load conditions automatically leads to a burst mode
operation allowing voltage regulation on the secondary side. The transition from normal
operation to burst mode operation happens for a power P
STBY
given by :
Where:
L
P
is the primary inductance of the transformer. F
SW
is the normal switching frequency.
I
STBY
is the minimum controllable current, corresponding to the minimum on time that the
device is able to provide in normal operation. This current can be computed as :
t
b
+ t
d
is the sum of the blanking time and of the propagation time of the internal current sense
and comparator, and represents roughly the minimum on time of the device. Note: that PSTBY
may be affected by the efficiency of the converter at low load, and must include the power
drawn on the primary auxiliary voltage.
P
STB Y
1
2
---L
P
I
2
STBY
F
SW=
I
STB Y
t
b
t
d
+()V
IN
L
p
-----------------------------=
5 Operation Description VIPer100-E
12/29
As soon as the power goes below this limit, the auxiliary secondary voltage starts to increase
above the 13V regulation level, forcing the output voltage of the transconductance amplifier to
low state (V
COMP
< V
COMPth
). This situation leads to the shutdown mode where the power
switch is maintained in the Off state, resulting in missing cycles and zero duty cycle. As soon as
V
DD
gets back to the regulation level and the V
COMPth
threshold is reached, the device
operates again. The above cycle repeats indefinitely, providing a burst mode of which the
effective duty cycle is much lower than the minimum one when in normal operation. The
equivalent switching frequency is also lower than the normal one, leading to a reduced
consumption on the input main supply lines. This mode of operation allows the VIPer100-E to
meet the new German "Blue Angel" Norm with less than 1W total power consumption for the
system when working in stand-by mode. The output voltage remains regulated around the
normal level, with a low frequency ripple corresponding to the burst mode. The amplitude of this
ripple is low, because of the output capacitors and low output current drawn in such
conditions.The normal operation resumes automatically when the power gets back to higher
levels than P
STBY
.
5.3 High Voltage Start-up Current Suorce
An integrated high voltage current source provides a bias current from the DRAIN pin during
the start-up phase. This current is partially absorbed by internal control circuits which are
placed into a standby mode with reduced consumption and also provided to the external
capacitor connected to the V
DD
pin. As soon as the voltage on this pin reaches the high voltage
threshold V
DDon
of the UVLO logic, the device becomes active mode and starts switching. The
start-up current generator is switched off, and the converter should normally provide the
needed current on the V
DD
pin through the auxiliary winding of the transformer, as shown on
(see Figure 11).
In case there are abnormal conditions where the auxiliary winding is unable to provide the low
voltage supply current to the V
DD
pin (i.e. short circuit on the output of the converter), the
external capacitor discharges to the low threshold voltage V
DDoff
of the UVLO logic, and the
device goes back to the inactive state where the internal circuits are in standby mode and the
start-up current source is activated. The converter enters a endless start-up cycle, with a start-
up duty cycle defined by the ratio of charging current towards discharging when the VIPer100-
E tries to start. This ratio is fixed by design to 2A to 15A, which gives a 12% start-up duty cycle
while the power dissipation at start-up is approximately 0.6W, for a 230Vrms input voltage.
This low value start-up duty cycle prevents the application of stress to the output rectifiers as
well as the transformer when a short circuit occurs.
The external capacitor C
VDD
on the V
DD
pin must be sized according to the time needed by the
converter to start up, when the device starts switching. This time t
SS
depends on many
parameters, among which transformer design, output capacitors, soft start feature, and
compensation network implemented on the COMP pin. The following formula can be used for
defining the minimum capacitor needed:
where:
I
DD
is the consumption current on the V
DD
pin when switching. Refer to specified I
DD1
and I
DD
2
values.
t
SS
is the start up time of the converter when the device begins to switch. Worst case is
generally at full load.
C
VDD
I
DD
t
SS
V
DDhys t
-------------------->

VIPER100-E

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
AC/DC Converters 620V 3A SMPS
Lifecycle:
New from this manufacturer.
Delivery:
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