VS-VSK.230..PbF Series
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Vishay Semiconductors
Revision: 27-Apr-17
2
Document Number: 93053
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ON-STATE CONDUCTION
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Maximum average on-state current
at case temperature
I
T(AV)
180° conduction, half sine wave
230 A
85 °C
Maximum RMS on-state current I
T(RMS)
As AC switch 510
A
Maximum peak, one-cycle on-state
non-repetitive, surge current
I
TSM
t = 10 ms
No voltage
reapplied
Sinusoidal
half wave,
initial
T
J
= T
J
maximum
7500
t = 8.3 ms 7850
t = 10 ms
100 % V
RRM
reapplied
6300
t = 8.3 ms 6600
Maximum I
2
t for fusing I
2
t
t = 10 ms
No voltage
reapplied
280
kA
2
s
t = 8.3 ms 256
t = 10 ms
100 % V
RRM
reapplied
198
t = 8.3 ms 181
Maximum I
2
√t for fusing I
2
√t t = 0.1 ms to 10 ms, no voltage reapplied 2800 kA
2
√s
Low level value or threshold voltage V
T(TO)1
(16.7 % x π x I
T(AV)
< I < π x I
T(AV)
), T
J
= T
J
maximum 1.03
V
High level value of threshold voltage V
T(TO)2
(I > π x I
T(AV)
), T
J
= T
J
maximum 1.07
Low level value on-state slope resistance r
t1
(16.7 % x π x I
T(AV)
< I < π x I
T(AV)
), T
J
= T
J
maximum 0.77
mΩ
High level value on-state slope resistance r
t2
(I > π x I
T(AV)
), T
J
= T
J
maximum 0.73
Maximum on-state voltage drop V
TM
I
TM
= π x I
T(AV)
, T
J
= T
J
maximum, 180° conduction,
average power = V
T(TO)
x I
T(AV)
+ r
f
x (I
T(RMS)
)
2
1.59 V
Maximum holding current I
H
Anode supply = 12 V, initial I
T
= 30 A, T
J
= 25 °C 500
mA
Maximum latching current I
L
Anode supply = 12 V, resistive load = 1 Ω,
gate pulse: 10 V, 100 μs, T
J
= 25 °C
1000
SWITCHING
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Typical delay time t
d
T
J
= 25 °C, gate current = 1 A dI
g
/dt = 1 A/μs,
V
d
= 0.67 % V
DRM
1.0
μs
Typical rise time t
r
2.0
Typical turn-off time t
q
I
TM
= 300 A; dI/dt = 15 A/μs; T
J
= T
J
maximum;
V
R
= 50 V; dV/dt = 20 V/μs; gate 0 V, 100 Ω
50 to 150
BLOCKING
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Maximum peak reverse and
off-state leakage current
I
RRM,
I
DRM
T
J
= T
J
maximum 50 mA
RMS insulation voltage V
INS
50 Hz, circuit to base, all terminals shorted, 25 °C, 1 s 3000 V
Critical rate of rise of off-state voltage dV/dt T
J
= T
J
maximum, exponential to 67 % rated V
DRM
1000 V/μs
TRIGGERING
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Maximum peak gate power P
GM
t
p
≤ 5 ms, T
J
= T
J
maximum 10.0
W
Maximum average gate power P
G(AV)
f = 50 Hz, T
J
= T
J
maximum 2.0
Maximum peak gate current + I
GM
t
p
≤ 5 ms, T
J
= T
J
maximum 3.0 A
Maximum peak negative gate voltage - V
GT
t
p
≤ 5 ms, T
J
= T
J
maximum 5.0
V
Maximum required DC gate voltage to trigger V
GT
T
J
= -40 °C
Anode supply = 12 V,
resistive load; Ra = 1 Ω
4.0
T
J
= 25 °C 3.0
T
J
= T
J
maximum 2.0
Maximum required DC gate current to trigger I
GT
T
J
= - 40 °C
Anode supply = 12 V,
resistive load; Ra = 1 Ω
350
mAT
J
= 25 °C 200
T
J
= T
J
maximum 100
Maximum gate voltage that will not trigger V
GD
T
J
= T
J
maximum, rated V
DRM
applied 0.25 V
Maximum gate current that will not trigger I
GD
T
J
= T
J
maximum, rated V
DRM
applied 10.0 mA
Maximum rate of rise of turned-on current dI/dt T
J
= T
J
maximum, I
TM
= 400 A, rated V
DRM
applied 500 A/μs
