LTC4224-1/LTC4224-2
10
422412fa
APPLICATIONS INFORMATION
If there is signifi cant supply lead inductance, a severe
output short may collapse the input to ground before the
LTC4224 can bring the current under control. In this case,
the undervoltage lockout activates after an 8µs fi lter delay,
and the GATE is pulled down by 1.5mA.
Resetting Faults
Following an overcurrent fault, the LTC4224-1 latches
off while the LTC4224-2 automatically restarts after a
four second cool down period. An overcurrent fault on
either supply causes the ECB for that supply to turn off
the MOSFET and pull the FAULT pin low. Faults are reset
by pulling the ON pin high for at least 20µs, after which
the FAULT pin releases and the turn-on sequence begins.
Taking the lower supply below V
CCLO(UVL)
clears only that
supplys fault and the turn-on sequence commences im-
mediately. Pulling the higher supply below V
CC(UVL)
clears
both supplies’ faults and the turn-on sequence begins after
a 160ms UV turn-on delay. When both supplies are above
2.5V, either supply going low only resets its own fault.
For the auto-retry version (LTC4224-2), if the fault is not
cleared within four seconds, the latched fault will be cleared
automatically. FAULT will go high and the turn-on sequence
will begin. A persistent fault results in an auto-retry duty
cycle of about 0.1%. Figure 9 shows an auto-retry sequence
as a result of an overcurrent fault.
Gate Pin Voltage
The gate drive is compatible with logic level MOSFETs, but
caution is required if one supply is low. The guaranteed
range of gate drive is 4.5V to 7V, with a typical value of
5.5V. Each GATE pin is clamped with respect to V
CC
, the
higher of the two input supplies. When V
CC
is at 5V, both
GATE pins can be as high as 12V above ground. If the
lower supply is at 0V, the gate-to-source voltage of its
MOSFET can be 12V. In such applications, MOSFETs with
gate-to-source breakdown ratings of 12V or greater are
recommended.
Active Current Loop Compensation
The active current loop is compensated by the parasitic
capacitance of the external MOSFET. No further compensa-
tion components are normally required. In the case where a
MOSFET with less than 600pF of gate capacitance is chosen,
a 600pF compensation capacitor connected between the
GATE pin and ground may be required.
Supply Transient Protection
In applications where the supply inputs are fed directly
from the regulated output of the backplane supply, bulk
bypassing assures a spike-free operating environment.
In other applications where bulk bypassing is located far
from the LTC4224, spikes generated during output short-
circuit events could exceed the absolute maximum ratings
for V
CC
. To minimize such spikes, use wider traces or
heavier trace plating to reduce the power trace inductance.
Figure 10. Input Supply Transient Protection
Network for Applications without Input Capacitance
422412 F10
LTC4224
V
CC2
GND
SENSE2
GATE2
R2
0.010Ω
V
CC2
V
OUT
C
LOAD2
Q2
FDS6911
+
R
SNUB
10Ω
C
SNUB
0.1µF
Z1
SMAJ5.0A
Figure 9. Auto-Retry After Overcurrent Fault
1s/DIV
I
OUT
1A/DIV
GATE
2V/DIV
FAULT
5V/DIV
422412 F09
LTC4224-1/LTC4224-2
11
422412fa
APPLICATIONS INFORMATION
Figure 11. Recommended Layout for Input
Supply Transient Protection Network
422412 F11
R
SNUB
C
SNUB
LTC4224
1
V
CC2
GATE2
GND
2
SENSE2
3
4
5
10
9
8
7
6
Z1
V
CC2
SNUBBER
NETWORK
VIAS TO
GND PLANE
PCB layout for the sense resistors and the power MOSFETs
should include good thermal management techniques for
optimal device power dissipation. A recommended PCB
layout for the sense resistors and the power MOSFET
around the LTC4224 is illustrated in Figure 12. Note that
it is important to keep the trace from the LTC4224’s GATE
pin to the FDS6911’s gate short.
In Hot Swap applications where load currents can be 10A,
wide PCB traces are recommended to minimize resistance
and temperature rise. The suggested trace width for 1oz
copper foil is 0.03" for each ampere of DC current to keep
PCB trace resistance, voltage drop and temperature rise to
a minimum. Note that the sheet resistance of 1oz copper
foil is approximately 0.5m/square and voltage drops
due to trace resistances add up quickly in high current
applications.
In most applications, it is necessary to use plated-through
vias to make circuit connections from component layers to
power and ground layers internal to the PCB. For 1oz cop-
per foil plating, a general rule is 1A of DC current per via.
Consult your PCB fabrication facility for design rules
pertaining to other plating thicknesses.
Design Example
As a design example, consider the following specifi cations:
V
CC1
= 5V, V
CC2
= 3.3V, I
LOAD1(MAX)
= 1A, I
LOAD2(MAX)
= 2A,
C
LOAD1
= C
LOAD2
= 150F (see Figure 1).
First, select the sense resistor for each supply. Calculate
the R1 and R2 values based on the maximum load cur-
rent and the minimum circuit breaker threshold limit,
ΔV
SENSE(CB)(MIN)
.
If a 1% tolerance is assumed for the sense resistors, then
the following values of resistance should suffi ce:
Table 2. Sense Resistor Values
SUPPLY VOLTAGE R
SENSE
(1%) I
TRIP(MIN)
I
TRIP(MAX)
5V 15m 1.49A 1.85A
3.3V 10m 2.23A 2.78A
For proper operation, I
TRIP(MIN)
must exceed the maxi-
mum load current with margin, so R
SENSE1
= 15mΩ and
R
SENSE2
= 10mΩ should suffi ce for the V
CC1
and V
CC2
supplies respectively.
Figure 12. Recommended Layout for
Power MOSFET and Sense Resistors
422412 F12
TOP SIDE
FDS6911
BOTTOM SIDE
LTC4224
11
6
8
7
9
10
5
4
2
3
1
5
6
4
3
7
8
2
1
5V3.3V
R2 R1
Also, bypass locally with a 10F electrolytic and 100nF
ceramic, or alternatively clamp the input with a transient
voltage suppressor (Z1) as shown in Figure 10. A 10,
100nF snubber damps the response and eliminates ring-
ing. A recommended layout of the transient protection
devices Z1, R
SNUB
and C
SNUB
around the LTC4224 is
shown in Figure 11.
PCB Layout Considerations
For proper operation of the LTC4224’s electronic circuit
breaker, Kelvin connections to the sense resistors are
strongly recommended. The PCB layout should be balanced
and symmetrical to minimize wiring errors. In addition, the
LTC4224-1/LTC4224-2
12
422412fa
APPLICATIONS INFORMATION
Next, assume that there is no load current at start-up,
and calculate the inrush current required to charge the
load capacitor. As there is no gate capacitor, the supplies
start-up in current limit. Compute the time, t
SU
, it takes
to fully charge the load capacitor:
t
SU
=
V
CC
•C
LOAD
I
TRIP
Table 3 lists the worst-case t
SU
values assuming 30%
tolerance for load capacitances.
Table 3. Worst-Case t
SU
VOLTAGE SUPPLY t
SU(MIN)
t
SU(MAX)
5V 0.53ms 0.65ms
3.3V 0.23ms 0.29ms
The start-up ECB blanking delay is guaranteed to be at least
2.5ms, which is longer than the t
SU
tabulated in Table 3.
Hence, both supplies can start up successfully.
Next, verify that the thermal ratings of the selected external
MOSFETs are not exceeded during power-up or an output
short-circuit. Assuming the MOSFET dissipates power only
due to inrush current charging the load capacitor, the energy
dissipated in the MOSFET during power-up is the same
as that stored in the load capacitor after power-up. The
average power dissipated in the MOSFET is given by:
P
AVG
=
C
LOAD
•V
OUT
2
2•t
SU
The worst-case P
AVG
is calculated to be 4.6W for both the 5V
supply and the 3.3V supply. In this example, the FDS6911
MOSFET offers a good solution. Since this MOSFET is a dual
N-channel in a single SO8 package, it must be able to tolerate
the combined power dissipation of both supplies during
the t
SU
start-up time. The increase in steady-state junction
temperature due to power dissipated in the MOSFET is
ΔT = P
AVG
•Z
TH
where Z
TH
is the thermal impedance.
Under this condition, the FDS6911 datasheet’s Transient
Thermal Impedance plot indicates that the junction tem-
perature will increase by 6.4°C using Z
THJC
= 0.7°C/W
(single pulse). The FDS6911’s on-resistance is 17m at
V
GS
= 4.5V, 25°C.
The magnitude of the power pulse that results during a
severe overload is calculated to be 9.25W for the 5V sup-
ply and 9.2W for the 3.3V supply under the worst case
conditions. Assuming a worst-case circuit breaker timeout
period of 7.5ms, the junction temperature will increase by
25°C, with one supply short-circuited. If both supplies are
short-circuited, the junction temperature will increase by
50°C in the worst-case. During auto-retry (LTC4224-2), in
the event of persistent faults at both supplies, the ample
four second cooling delay limits the increase in junction
temperature to 50°C. The SOA curves of the FDS6911
indicate that the above conditions are safe.

LTC4224CMS-1#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Compact 2x L V Hot Swap Cntr
Lifecycle:
New from this manufacturer.
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