LTC4224-1/LTC4224-2
7
422412fa
APPLICATIONS INFORMATION
V
CC
Selection
The LTC4224 is powered from the higher of its two supply
pins, V
CC1
and V
CC2
.This allows the part to control a sup-
ply voltage as low as 1V, while the other supply is 2.7V or
greater. If both supplies are tied together, the part derives
its power from both equally. The Functional Diagram shows
the V
CC
selection circuit in an ideal diode OR-ing arrange-
ment. It is designed to ensure swift and smooth internal
power switchover from one supply to the other.
Turn-On Sequence
Separate ON1 and ON2 pins allow the V
CC1
and V
CC2
supplies to be turned on in any order. The power supplies
delivered to a plug-in card are controlled by external N-
channel MOSFETs, Q1 and Q2. For X2/XENPAK defi ned
optical transceiver modules, it has been specifi ed that the
MOD DETECT pin pulls low inside the module through a
1k resistor (R
MOD_DET
), as shown in Figure 1. Several
conditions must be satisfi ed to turn on the MOSFETs.
First, V
CC1
or V
CC2
must exceed the 2.4V V
CC
undervoltage
lockout level for longer than an internal UV turn-on delay
of 160ms. Next, if V
CCn
is greater than 0.8V and ONn is
low (<0.8V), a debounce delay of 10ms is started. If V
CCn
drops below 0.8V or ONn goes high before the end of the
10ms debounce delay, the debounce delay is restarted the
next time these pins are properly conditioned.
When the 10ms debounce delay expires, the external
MOSFET is turned on by charging up the GATE with a
Figure 2. Normal Power-Up Sequence
V
OUT1
5V/DIV
V
OUT2
5V/DIV
5ms/DIV
422412 F02
ON1/2
2V/DIV
GATE1
5V/DIV
GATE2
5V/DIV
10µA charge pump generated current source. When the
GATE voltage reaches the MOSFET threshold voltage, the
inrush current can build up quickly as the GATE continues
to rise. The ACL amplifi er actively controls the gate volt-
age to maintain 25mV across the sense resistor. In this
condition, the inrush current is given by:
I
INRUSH
=
25mV
R
SENSE
As the inrush current charges up the load capacitor, the
output rises with a corresponding increase in gate voltage.
When the supply is no longer in current limit, an internal
charge pump pulls the gate to 5.5V above the higher of V
CC1
or V
CC2
to achieve a low resistance power path. Figure 2
shows a typical start-up sequence with C
LOAD1
= C
LOAD2
= 150µF, R
LOAD1
= 4.7Ω and R
LOAD2
= 2Ω.
The inrush current can be reduced to below the current
limit level by adding an external gate capacitor as shown
in Figure 3.
GATE capacitor C
GATE
provides gate slew rate control to limit
the inrush current. However, C
GATE
could cause parasitic
high frequency self oscillation in Q1. A 10Ω resistor, R
G
, as
shown in Figure 3 can be used to prevent the oscillation.
To be effective, R
G
needs to be laid out close to Q1.
The voltage at the GATE pin rises with a slope equal to I
GATE
/
C
GATE
. For a given supply inrush current I
INRUSH
and load
capacitor C
LOAD
, C
GATE
can be calculated according to:
C
GATE
=
I
GATE
I
INRUSH
•C
LOAD
Figure 3. Inrush Current Control by Gate Capacitor
422412 F03
LTC4224
V
CC1
SENSE1
GATE1
R1
0.015Ω
5V
I
GATE
C
GATE
R
G
10Ω
C
LOAD
Q1
LTC4224-1/LTC4224-2
8
422412fa
APPLICATIONS INFORMATION
If the voltage across the sense resistor R1 becomes too
high, the inrush current is limited by the internal current
limit circuitry.
Turn-Off Sequence
The MOSFETs can be turned off by the conditions sum-
marized in Table 1.
Table 1. Turn-Off Conditions
CONDITION
RESULT
CHANNEL 1 CHANNEL 2 CLEARED BY
ON1 Goes High Turns Off No Effect ON1 Low
ON2 Goes High No Effect Turns Off ON2 Low
UVLO on V
CC
Turns Off Turns Off V
CC
> UVLO
UVLO on V
CC1
Turns Off No Effect V
CC1
> UVLO
UVLO on V
CC2
No Effect Turns Off V
CC2
> UVLO
CH1 Overcurrent Fault Turns Off No Effect ON1 High,
UVLO on V
CC1
CH2 Overcurrent Fault No Effect Turns Off ON2 High,
UVLO on V
CC2
When ON1 or ON2 is pulled high, the corresponding GATE
pin is pulled to ground by 1.5mA. With the MOSFET off,
the load current discharges the load capacitor. Figure 4
shows V
CC1
supply turning off by pulling ON1 high with
R
LOAD1
= 4.7Ω discharging C
LOAD1
= 150µF.
Overcurrent Fault
The LTC4224 features an adjustable current limit with circuit
breaker function that protects external MOSFETs against
short circuits or excessive load current. The voltage across
the external sense resistor is monitored by the active cur-
rent limit (ACL) amplifi er and the electronic circuit breaker
(ECB) comparator. An overcurrent condition results in the
current being limited by the ACL amplifi er. During current
limiting, the ECB is activated and initiates a chain of logic
and timing events to handle the fault.
Figure 5 illustrates the LTC4224’s response to an overcurrent
condition on one supply output. Start-up and overcurrent
control for the two supplies are independent. Before time
point t
1
, the ON pin is high and the part is in reset. When
the ON pin goes low, a 10ms debounce delay is started.
After 10ms (time point t
2
), the external MOSFET is turned
on by charging GATE with 10µA. The load capacitor starts
to charge up and the output voltage increases. At the same
Figure 4. Normal Power-Down Sequence
Figure 5. Fault Handling Sequence
0.2ms/DIV
ON1
2V/DIV
V
OUT1
5V/DIV
GATE1
5V/DIV
422412 F04
422412 F05
5ms ECB Arm
RESET
t
3
t
2
t
1
t
6
t
5
t
4
IDLE
OVERCURRENT 5ms
ECB BLANKING DELAY
5ms START-UP
BLANKING DELAY
10ms DEBOUNCE DELAY
ON
FAULT
V
OUT
I
OUT
I
LIMIT
I
LIMIT
LTC4224-1/LTC4224-2
9
422412fa
APPLICATIONS INFORMATION
time, a 5ms start-up blanking delay begins during which
the circuit breaker is not allowed to latchoff the MOSFET.
If the ECB is tripped at the end of 5ms (time point t
3
), the
MOSFET is latched off by pulling GATE down with 1.5mA
and FAULT is latched low. The waveform in Figure 6 shows
an unsuccessful start-up due to a short circuit at the output.
To ensure start-up, the load capacitor must be charged
up suffi ciently to exit current limit before the end of the
5ms blanking delay. For large load capacitors, it may be
necessary to connect an external capacitor from GATE to
GND as described in the Turn-On Sequence section.
After start-up, any transient overcurrent faults lasting
less than 100µs are ignored. Any overcurrent condition
lasting more than 100µs will initiate the 5ms ECB blank-
ing delay (time point t
4
). After the ECB blanking delay,
the ECB is armed for the following 5ms (time point t
5
to
t
6
). Any 100µs overcurrent pulse during this time latches
off the MOSFET. In summary, for 5ms to 10ms after a
100µs or greater overcurrent fault is detected, a second
100µs fault condition causes the MOSFET to latchoff. If
no overcurrent condition is detected during this time, the
part re-enters the IDLE state and another blanking delay
following an overcurrent condition is again required before
the MOSFET latches off. Figure 7 shows how the output
latches off following an overcurrent fault.
During a severe short-circuit (see Figure 8), the output load
current can briefl y surge to tens of amperes. The LTC4224
rapidly brings the current under control by discharging
the MOSFETs gate with 125mA towards ground. After a
short delay, the ACL amplifi er regulates the gate voltage
until the ECB trips at the end of 5ms.
Undervoltage Fault
An undervoltage fault occurs if either V
CC1
or V
CC2
falls
below 0.8V for longer than 8s. This turns off the affected
supplys switch by discharging GATE with 1.5mA and
clears its fault latch. An undervoltage fault on one supply
does not affect the operation of the other supply. If V
CC
,
the higher of V
CC1
and V
CC2
, falls below 2.4V for more
than 12s, all supply switches are turned off and all fault
latches are cleared.
Figure 6. Start-Up with Short at Output
5ms/DIV
ON1
2V/DIV
FAULT
5V/DIV
I
OUT1
1A/DIV
GATE1
5V/DIV
422412 F06
Figure 8. Severe Short-Circuit on Output
0.5µs/DIV
I
OUT2
8A/DIV
V
OUT2
5V/DIV
GATE2
5V/DIV
422412 F08
Figure 7. Overcurrent Fault on Output
2ms/DIV
I
OUT1
1A/DIV
V
OUT1
5V/DIV
GATE1
5V/DIV
422412 F07

LTC4224CMS-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Compact 2x L V Hot Swap Cntr
Lifecycle:
New from this manufacturer.
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