CS51033
http://onsemi.com
8
6) Divider Bypass Capacitor C
RR
Since the feedback resistors divide the output voltage by
a factor of 4.0, i.e. 5.0 V/1.25 V= 4.0, it follows that the
output ripple is also divided by four. This would require that
the output ripple be at least 60 mV (4.0 × 15 mV) to trip the
feedback comparator. We use a capacitor C
RR
to act as an
AC short so that the output ripple is not attenuated by the
divider network. The ripple voltage frequency is equal to the
switching frequency so we choose C
RR
so that:
X
C
+
1.0
2pfC
is negligible at the switching frequency.
In this case F
SW
is 200 kHz if we allow X
C
= 3.0 W then:
C +
1.0
2pf3
^ 0.265 mF
7) Soft−Start and Fault Timing Capacitor CS
CS performs several important functions. First it provides
a dead time for load transients so that the IC does not enter
a fault mode every time the load changes abruptly. Secondly
it disables the fault circuitry during startup, it also provides
Soft−Start by clamping the reference voltage during startup
to rise slowly and finally it controls the hiccup short circuit
protection circuitry. This function reduces the P−Ch FET’s
duty cycle to 2.0% of the CS period.
The most important consideration in calculating CS is that
it’s voltage does not reach 2.5 V (the voltage at which the
fault detect circuitry is enabled) before V
FB
reaches 1.15 V
otherwise the power supply will never start.
If the V
FB
pin reaches 1.15 V, the fault timing comparator
will discharge CS and the supply will not start. For the V
FB
voltage to reach 1.15 V the output voltage must be at least
4 × 1.15 = 4.6 V.
If we choose an arbitrary startup time of 200 ms, we
calculate the value of CS from:
T +
CS 2.5 V
I
CHARGE
CS
(MIN)
+
200 ms 264 mA
2.5 V
+ 0.02 mF
Use 0.1 mF.
The fault time out time is the sum of the slow discharge
time the fast discharge time and the recharge time and is
obviously dominated by the slow discharge time.
The first parameter is the slow discharge time, it is the time
for the CS capacitor to discharge from 2.4 V to 1.5 V and is
given by:
T
SLOWDISCHARGE
+
CS
(
2.4 V * 1.5 V
)
I
DISCHARGE
where I
DISCHARGE
is 6.0 mA typical.
T
SLOWDISCHARGE
+ CS 1.5 V 10
5
The fast discharge time occurs when a fault is first
detected. The CS capacitor is discharged from 2.5 V to 2.4 V.
T
FASTDISCHARGE
+
CS
(
2.5 V * 2.4 V
)
I
FASTDISCHARGE
where I
FASTDISCHARGE
is 66 mA typical.
T
FASTDISCHARGE
+ CS 1515
The recharge time is the time for CS to charge from 1.5 V
to 2.5 V.
T
CHARGE
+
CS
(
2.5 V * 1.5 V
)
I
CHARGE
where I
CHARGE
is 264 mA typical.
T
CHARGE
+ CS 3787
The fault time out time is given by:
T
FAULT
+ CS
(
3787 ) 1515 ) 1.5 10
5
)
T
FAULT
+ CS
(
1.55 10
5
)
For this circuit
T
FAULT
+ 0.1 10
*6
1.55 10
5
+ 0.0155
A larger value of CS will increase the fault time out time
but will also increase the Soft−Start time.
8) Input Capacitor
The input capacitor reduces the peak currents drawn from
the input supply and reduces the noise and ripple voltage on
the V
CC
and V
C
pins. This capacitor must also ensure that
the V
CC
remains above the UVLO voltage in the event of an
output short circuit. C
IN
should be a low ESR capacitor of
at least 100 mF. A ceramic surface mount capacitor should
also be connected between V
CC
and ground to prevent
spikes.
9) MOSFET Selection
The CS51033 drives a P−Channel MOSFET. The V
GATE
pin swings from GND to V
C
. The type of P−Ch FET used
depends on the operating conditions but for input voltages
below 7.0 V a logic level FET should be used.
Choose a P−Ch FET with a continuous drain current (I
D
)
rating greater than the maximum output current. R
DS(ON)
should be less than
R
DS
t+
0.6 V
I
OUT(MAX)
167 mW
The Gate−to−Source voltage V
GS
and the
Drain−to−Source Breakdown Voltage should be chosen
based on the input supply voltage.
The power dissipation due to the conduction losses is
given by:
P
D
+ I
OUT
2
R
DS(ON)
D
The power dissipation due to the switching losses is given
by:
P
D
+ 0.5 V
IN
I
OUT
(
T
R
r
) T
F
)
F
SW
where T
R
= Rise Time and T
F
= Fall Time
.
