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74LVCH16374APAG

P1-P3P4-P6
INDUSTRIAL TEMPERATURE RANGE
IDT74LVCH16374A
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
1
OCTOBER 2015INDUSTRIAL TEMPERATURE RANGE
IDT and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4643/5
FEATURES:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
•VCC = 3.3V ± 0.3V, Normal Range
•VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4
μμ
μμ
μ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
IDT74LVCH16374A
DESCRIPTION
The LVCH16374A 16-bit edge-triggered D-type register is built using
advanced dual metal CMOS technology. This high-speed, low-power
register is ideal for use as a buffer register for data synchronization and
storage. The Output Enable (OE) and clock (CLK) controls are organized
to operate each device as two 8-bit registers or one 16-bit register with
common clock. Flow-through organization of signal pins simplifies layout. All
inputs are designed with hysteresis for improved noise margin.
All pins of the LVCH16374A can be driven from either 3.3V or 5V devices.
This feature allows the use of this device as a translator in a mixed 3.3V/5V
supply system.
The LVCH16374A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16374A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
3.3V CMOS 16-BIT
EDGE-TRIGGERED D-TYPE FLIP-
FLOP WITH 3-STATE OUTPUTS,
5V TOLERANT I/O AND BUS-HOLD
1OE
1CLK
1D1
1
Q1
TO SEVEN OTHER CHANNELS
2OE
2CLK
2D1
2
Q1
1
48
47
2
24
25
36
13
C1
1
D
1D
C
1
TO SEVEN OTHER CHANNELS
INDUSTRIAL TEMPERATURE RANGE
2
IDT74LVCH16374A
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
SSOP / TSSOP
TOP VIEW
PIN CONFIGURATION
Symbol Description Max Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –50 to +50 mA
I
IK Continuous Clamp Current, –50 mA
IOK VI < 0 or VO < 0
I
CC Continuous Current through each ±100 mA
ISS VCC or GND
ABSOLUTE MAXIMUM RATINGS
(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. As applicable to the device type.
Symbol Parameter
(1)
Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 4.5 6 pF
COUT Output Capacitance VOUT = 0V 6.5 8 pF
C
I/O I/O Port Capacitance VIN = 0V 6.5 8 pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
NOTES:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
↑ = LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established.
Inputs Outputs
xDx xCLK xOE xQx
H ↑ LH
L ↑ LL
X H or L L Q
(2)
XX H Z
FUNCTION TABLE (EACH FLIP-FLOP)
(1)
Pin Names Description
xDx Data Inputs
(1)
xCLK Clock Inputs
xOE Output Enable Inputs (Active LOW)
x Q x 3-State Outputs
PIN DESCRIPTION
1Q2
GND
V
CC
GND
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
40
41
42
43
44
45
46
47
481
1Q1
1
OE
1Q4
1
Q3
1
Q6
1
Q5
1
Q8
1
Q7
2
Q1
2
Q3
2
Q2
2
Q4
VCC
2Q5
2
Q6
GND
2Q7
2
Q8
2
OE
1D2
GND
V
CC
GND
GND
1D1
1
CLK
1D4
1D3
1
D6
1
D5
1
D8
1
D7
2
D1
2
D3
2
D2
2
D4
VCC
2D5
2
D6
GND
2D7
2
D8
2
CLK
INDUSTRIAL TEMPERATURE RANGE
IDT74LVCH16374A
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
3
Symbol Parameter Test Conditions Min. Typ.
(1)
Max. Unit
VIH Input HIGH Voltage Level VCC = 2.3V to 2.7V 1.7 — — V
VCC = 2.7V to 3.6V 2 — —
V
IL Input LOW Voltage Level VCC = 2.3V to 2.7V — — 0.7 V
VCC = 2.7V to 3.6V — — 0.8
IIH Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 μA
IIL
IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 μA
IOZL (3-State Output pins)
IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 μA
VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V
VH Input Hysteresis VCC = 3.3V — 100 — mV
I
CCL Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC —— 10μA
ICCH
ICCZ 3.6 ≤ VIN ≤ 5.5V
(2)
—— 10
ΔICC Quiescent Power Supply Current One input at VCC - 0.6V, other inputs at VCC or GND — — 500 μA
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol Parameter
(1)
Test Conditions Min. Typ.
(2)
Max. Unit
IBHH Bus-Hold Input Sustain Current VCC = 3V VI = 2V – 75 — — μA
IBHL VI = 0.8V 75 — —
IBHH Bus-Hold Input Sustain Current VCC = 2.3V VI = 1.7V — — — μA
IBHL VI = 0.7V — — —
IBHHO Bus-Hold Input Overdrive Current VCC = 3.6V VI = 0 to 3.6V — — ±500 μA
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
P1-P3P4-P6

74LVCH16374APAG

Mfr. #:
Buy 74LVCH16374APAG
Manufacturer:
IDT
Description:
Flip Flops 16-bit Edge-Trig D-Type Flip-Flop
Lifecycle:
New from this manufacturer.
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