PL602-XX
HCSL Compatible Clock Generator for PCI Express
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • t el +1(408) 94 4 -0800 • fax +1(408) 474-1000 • www.mi crel.com Rev 02/08/1 1 Page 4
PCI EXPRESS/HCSL COM PAT IBLE LAY OUT GUIDELINES
Figure 1 below describes how to terminate the complementary LVCMOS outputs of PL602-XX for use with HCSL
inputs.
50 Ohm line
50 Ohm line
Rs
Rs
Rt
Rt
LVCMOS Output
Complementary
LVCMOS Output
0V
3.3V
0V
0.75V
Complementary
Input
Input
Component Selection
For 3.3V Operation
Rs = 150 Ohm
Rt = 50 Ohm
Notes:
Place Rs as close to the LVCMOS outputs as possible.
Place Rt as close to the HCSL inputs as possible.
HCSL
Figure 1
For 2.5V Operation
Rs = 100 Ohm
Rt = 50 Ohm
PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION
The following guidelines are to assist you with a performance optimized PCB design:
- Keep all the PCB traces to PL602-XX as short as
possible, as well as keeping all other traces as far away
from it as possible.
- Place the crystal as close as possible to both crystal
pins of the device. This will reduce the cross-talk
between the crystal and the other signals.
- Separate crystal pin traces from the other signals on the
PCB, but allow ample distance between the two crystal
pin traces.
- Place a 0.01µF~0.1µF decoupling capacitor between
VDD and GND, on the component side of the PCB,
close to the VDD pin. It is not recommended to place
this component on the backside of the PCB.
- It is highly recommended to keep the VDD and GND
traces as short as possible.
- When connecting long traces (> 1 inch) to a CMOS
output, it is important to design the traces as a
transmission line or ‘stripline’, to avoid reflections or
ringing. In this case, the CMOS output needs to be
matched to the trace impedance. Usually ‘striplines’ are
designed for 50Ω impedance and CMOS outputs
usually have lower than 50Ω impedance so matching
can be achieved by adding a resistor in series with the
CMOS output pin to the ‘stripline’ trace.
