2013-2016 Microchip Technology Inc. DS20005215C-page 7
24AA256UID
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 4-2: ACKNOWLEDGE TIMING
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
Start
Condition
SCL
SDA
(A) (B) (D) (D) (C) (A)
SCL
987654321 123
Transmitter must release the SDA line at this point,
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
Data from transmitter
SDA
Acknowledge
Bit
Data from transmitter
24AA256UID
DS20005215C-page 8 2013-2016 Microchip Technology Inc.
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a 4-bit control code. For the
24AA256UID, this is set as ‘1010’ binary for read and
write operations. The next three bits of the control byte
are the Chip Select bits (A2, A1, A0). The Chip Select
bits allow the use of up to eight 24AA256UID devices
on the same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1 and A0 pins for the device to respond. These bits
are, in effect, the three Most Significant bits of the word
address.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’, a read operation is
selected. When set to0’, a write operation is selected.
The next two bytes received define the address of the
first data byte (Figure 5-2). Because only A14…A0 are
used, the upper address bits are “don’t cares”. The
upper address bits are transferred first, followed by the
Less Significant bits.
Following the Start condition, the 24AA256UID
monitors the SDA bus checking the device type
identifier being transmitted. Upon receiving a ‘1010
code and appropriate device select bits, the slave
device outputs an Acknowledge signal on the SDA line.
Depending on the state of the R/W
bit, the
24AA256UID will select a read or write operation.
FIGURE 5-1: CONTROL BYTE
FORMAT
5.1 Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 2 Mbit
by adding up to eight 24AA256UID devices on the
same bus. In this case, software can use A0 of the
control byte as address bit A15; A1 as address bit
A16; and A2 as address bit A17. It is not possible to
sequentially read across device boundaries.
FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS
10
1
0 A2 A1 A0
S
ACKR/W
Control Code
Chip Select
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write
Bit
1010
A
2
A
1
A
0
R/W x
A
11
A
10
A
9
A
7
A
0
A
8
••••••
A
12
Control Byte Address High Byte Address Low Byte
Control
Code
Chip
Select
Bits
x = “don’t care” bit
A
13
A
14
2013-2016 Microchip Technology Inc. DS20005215C-page 9
24AA256UID
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start condition from the master, the
control code (four bits), the Chip Select (three bits) and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the Address
Pointer of the 24AA256UID. The next byte is the Least
Significant Address Byte. After receiving another
Acknowledge signal from the 24AA256UID, the master
device will transmit the data word to be written into the
addressed memory location. The 24AA256UID
acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle and
during this time, the 24AA256UID will not generate
Acknowledge signals (Figure 6-1).
6.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24AA256UID in much the
same way as in a byte write. The exception is that
instead of generating a Stop condition, the master
transmits up to 63 additional bytes, which are
temporarily stored in the on-chip page buffer, and will
be written into memory once the master has
transmitted a Stop condition. Upon receipt of each
word, the six lower Address Pointer bits are internally
incremented by one. If the master should transmit more
than 64 bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-2).
6.3 Write Protection
The upper eighth of the array (7000h-7FFFh) is
permanently write-protected. Write operations to this
address range are inhibited. Read operations are not
affected.
The remainder of the array (0000h-6FFFh) can be
written to and read from normally.
Note: When doing a write of less than 64 bytes,
the data in the rest of the page is
refreshed along with the data bytes being
written. This will force the entire page to
endure a write cycle, and for this reason
endurance is specified per page.
Note: Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of [page size – 1]. If
a Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is, therefore, necessary for
the application software to prevent page
write operations that would attempt to
cross a page boundary.

24AA256UID-I/SN

Mfr. #:
Manufacturer:
Microchip Technology
Description:
EEPROM 256K I2C EE EUI-48 EUI-64 Unique ID
Lifecycle:
New from this manufacturer.
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