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ATPL210A-A1U-Y

P1-P3P4-P6P7-P9P10-P10
Atmel ATPL210A
PRIME compliant Power Line Communications SoC
SUMMARY DATASHEET
Features
• Core
• ADD8051C3A enhanced 8051 core
• Speedups up to x5 vs. standard 8051 microcontroller
• Modem
• Power Line Carrier Modem for 50 and 60 Hz mains
• 97-carrier OFDM PRIME compliant
• Baud rate Selectable: 21400 to 128600 bps
• Differential BPSK, QPSK, 8-PSK modulations
• Memories
• 32Kbytes on-chip SRAM
• Up to 256Kbytes external SRAM
• In-circuit serial flash programming
• Auto boot-loading program from serial flash
• Automatic Gain Control and signal amplitude tracking
• Embedded on-chip DMAs
• Automatic code encryption during boot loading
• Media Access Control
• Viterbi decoding and CRC PRIME compliant
• 128-bit AES encryption
• Channel sensing and collision pre-detection
• Peripherals
• Two 2-wire UARTs
• Two SPI. SPI to serial flash and External RTC. Buffered SPI to external metering
IC
• Programmable Watchdog
• Up to 14 I/O lines
• Package
• 120-lead LQFP, 14 x 14 mm, pitch 0.4 mm
• Pb-free and RoHS compliant
• Typical Applications
• Automated Meter Reading (AMR) & Advanced Meter Management (AMM)
• Street lighting
• Home Automation
43003A-ATPL-03/12
Atmel ATPL210A [summary datasheet]
43003A-ATPL-03/12
2
Description
The ATPL210 is a Power Line Communications System on Chip, which implements a
full PRIME compliant PLC modem. It includes an enhanced 8051 microcontroller (IP
core ADD8051C3A), a Medium Access Controller (MAC) (IP core ADD1221) and a
Modem circuit (IP core ADD1321) for power line medium using OFDM modulation
compatible with PRIME specifications.
ATPL210 is oriented to high performance & robust AMR systems. The ATPL210 is
designed to be used by meter manufacturers to provide a low cost and compact
solution for AMR & AMM systems using narrow band power line communications.
This device has been developed to reduce CPU computational load in PLC systems
running PRIME protocols. ATPL210 includes all necessary resources to be used as
main controller in metering applications, and allows an external device to
communicate according to PLC PRIME specifications.
Atmel ATPL210A [summary datasheet]
43003A-ATPL-03/12
3
1. Block Diagram
Figure 1-1. ATPL210A 120-pin Block Diagram
DEBUG
RESET
Clock
Reset
Interface
Clock
Interface
Power
Management
CODE
SRAM
BOOT
LOADER
SPI0
XDATA
SRAM
SPI1
UART0
UART1
TIMER2
T11, T12
WATCHDOG
MAC
Coprocessor
VSENSE
PSENSE
VNR
VIN
VRH
VRL
8051C3A Core
OFDM
PLC
MODEM
IDATA
32KB On-chip SRAM
D_INIT
RSTA
CLKA
CLKB
MISO0 , MOSI0,
SPI CLK0, SS0
MISO1 , MOSI1,
SPI CLK1, SS1
Rx0, Tx0
Rx1, Tx1
T2
VDD
VSSO
LDO _P D
VDEO
AVD AVS
/EWDG
DEB UG
/PROG
SEC URED
SSN
20MHz
AES
DMA
MEMORY
CONTROLLER
EX TRAM
A(0:17)
D(0:7)
/ R_WE
/ R_OE
/ R_CE
AFE_TX R X
AFE_HI MP
AGC1
EMIT(1:12)
JTAG
Bscan
TDI
TDO
TCK
TRST
TMS
AGC0
TIMER 0,1
GENERAL
PURPOSE I/O
P1.7
P3(0,1)
P4(2:6)
P5(0:5)
P1-P3P4-P6P7-P9P10-P10

ATPL210A-A1U-Y

Mfr. #:
Buy ATPL210A-A1U-Y
Manufacturer:
Microchip Technology / Atmel
Description:
Network Controller & Processor ICs 120LQFP, Rohs
Lifecycle:
New from this manufacturer.
Delivery:
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