ADM3307E/ADM3310E/ADM3311E/ADM3312E/ADM3315E Data Sheet
Rev. J | Page 16 of 20
The transmitter outputs and receiver inputs have a similar protec-
tion structure. The receiver inputs can also dissipate some of the
energy through the internal 5 kΩ (or 22 kΩ for the ADM3310E)
resistor to GND as well as through the protection diodes.
R
IN
Rx
D1
D2
RECEIVER
INPUT
02915-030
Figure 30. Receiver Input Protection Scheme
Tx
D1
D2
TRANSMITTER
OUTPUT
02915-031
Figure 31. Transmitter Output Protection Scheme
The ADM3307E protection scheme is slightly different (see
Figure 32 and Figure 33). The receiver inputs, transmitter
inputs, and transmitter outputs contain two back-to-back high
speed clamping diodes. The receiver outputs (CMOS outputs),
the SD and
EN
pins, contain a single reverse biased high speed
clamping diode. Under normal operation with maximum
CMOS signal levels, the receiver output, SD, and
EN
protection
diodes have no effect because they are reversed biased. If,
however, the voltage exceeds about 15 V, reverse breakdown
occurs and the voltage is clamped at this level. If the voltage
reaches −0.7 V, the diode is forward biased and the voltage is
clamped at this level. The receiver inputs can also dissipate
some of the energy through the internal 5 kΩ resistor to GND
as well as through the protection diodes.
R
IN
D1
D3
D2
RECEIVER
INPUT
RECEIVER
OUTPUT
Rx
02915-032
Figure 32. ADM3307E Receiver Input Protection Scheme
D1
D2
D3
D4
TRANSMITTER
OUTPUT
TRANSMITTER
INPUT
Tx
02915-033
Figure 33. ADM3307E Transmitter Output Protection Scheme
The protection structures achieve ESD protection up to ±15 kV
on all RS-232 I/O lines (and all CMOS lines, including SD and
EN
for the ADM3307E). For methods used to test the
protection scheme, see the ESD Testing (IEC 1000-4-2) section.
ESD TESTING (IEC 1000-4-2)
IEC 1000-4-2 (previously 801-2) specifies compliance testing
using two coupling methods, contact discharge and air-gap
discharge. Contact discharge calls for a direct connection to the
unit being tested. Airgap discharge uses a higher test voltage but
does not make direct contact with the unit under testing. With
air discharge, the discharge gun is moved toward the unit under
testing, which develops an arc across the air gap, thus the term
air discharge. This method is influenced by humidity,
temperature, barometric pressure, distance, and rate of closure
of the discharge gun. The contact discharge method, while less
realistic, is more repeatable and is gaining acceptance in
preference to the air-gap method.
Although very little energy is contained within an ESD pulse,
the extremely fast rise time coupled with high voltages can
cause failures in unprotected semiconductors. Catastrophic
destruction can occur immediately as a result of arcing or
heating. Even if catastrophic failure does not occur immediately,
the device can suffer from parametric degradation that can
result in degraded performance. The cumulative effects of
continuous exposure can eventually lead to complete failure.
I/O lines are particularly vulnerable to ESD damage. Simply
touching or plugging in an I/O cable can result in a static
discharge that can damage or completely destroy the interface
product connected to the I/O port. Traditional ESD test
methods, such as the MIL-STD-883B method 3015.7, do not
fully test a product’s susceptibility to this type of discharge. This
test was intended to test a product’s susceptibility to ESD
damage during handling.
Each pin is tested with respect to ground. There are some
important differences between the traditional test and the IEC
test.
The IEC test is much more stringent in terms of discharge
energy. The peak current injected is over four times
greater.
The current rise time is significantly faster in the IEC test.
The IEC test is carried out while power is applied to the
device.
It is possible that the ESD discharge could induce latch-up in
the device under test. This test, therefore, is more representative
of a real world I/O discharge where the equipment is operating
normally with power applied. For maximum peace of mind,
however, both tests should be performed, ensuring maximum
protection both during handling and later during field service.
Data Sheet ADM3307E/ADM3310E/ADM3311E/ADM3312E/ADM3315E
Rev. J | Page 17 of 20
R1
C1
ESD TEST METHOD R2 C1
IEC1000-4-2
1.5k 100pF
HUMAN BODY MODEL
ESD ASSOC. STD 55.1
330 150pF
DEVICE
UNDER TEST
HIGH
VOLTAGE
GENERATOR
R2
02915-034
Figure 34. ESD Test Standards
100
90
36.8
10
TIME t
t
DL
t
RL
I
PEAK
(%)
0
2915-035
Figure 35. Human Body Model ESD Current Waveform
100
90
10
TIME
t
30ns
60ns
0.1ns TO 1ns
I
PEAK
(%)
02915-036
Figure 36. IEC1000-4-2 ESD Current Waveform
The ADM3307E/ADM3310E/ADM3311E/ADM3312E/
ADM3315E devices are tested using both of the previously
mentioned test methods. All pins are tested with respect to all
other pins as per the Human Body Model, ESD Assoc. Std. 55.1
specification. In addition, all I/O pins are tested as per the IEC
1000-4-2 test specification. The products were tested under the
following conditions:
Power-On—Normal Operation
Power-Off
There are four levels of compliance defined by IEC 1000-4-2.
The ADM3307E/ADM3310E/ADM3311E/ADM3312E/
ADM3315E devices meet the most stringent compliance level
for both contact and air-gap discharge. This means the products
are able to withstand contact discharges in excess of 8 kV and
airgap discharges in excess of 15 kV.
Table 9. IEC 1000-4-2 Compliance Levels
Level Contact Discharge (kV) Air Discharge (kV)
1 2 2
2 4 4
3 6 8
4 8 15
ADM3307E/ADM3310E/ADM3311E/ADM3312E/ADM3315E Data Sheet
Rev. J | Page 18 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
112408-A
1
0.50
BSC
BOTT
OM VIEWTOP VIEW
PIN 1
INDIC
AT
OR
32
9
16
17
24
25
8
EXPOSED
PA
D
PIN 1
INDICATOR
3.25
3.10 SQ
2.95
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
0.30
0.25
0.18
5.10
5.00 SQ
4.90
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.50
0.40
0.30
0.25 MIN
Figure 37. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-7)
Dimensions shown in millimeters
COMPLIANT T
O JEDEC ST
ANDARDS MO-150-AH
060106-A
28
15
14
1
10.50
10.20
9.90
8.20
7.80
7.40
5.60
5.30
5.00
SE
ATING
PLANE
0.05 MIN
0.65 BSC
2.00 MAX
0.38
0.22
COPLANARITY
0.10
1.85
1.75
1.65
0.25
0.09
0.95
0.75
0.55
Figure 38. 28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters

ADM3311EARUZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RS-232 Interface IC 3V Serial Port Driver-Receiver
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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