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ISL8703AIBZ-T

P1-P3P4-P6P7-P9P10-P12
10
FN6381.0
October 12, 2006
Application Recommendations
Best practices V
IN
decoupling is required, a 1μF capacitor is
recommended.
Coupling from the ENABLE_X pins to the sensitive UV and
OV pins can cause false OV/UV events to be detected. This
is most relevant for ISL8700A, ISL8702A, ISL8704A parts
due to the ENABLEA and OV pins being adjacent. This
coupling can be reduced by adding a ground trace between
UV and the ENABLE/FAULT signals, as shown in Figure 15.
The PCB traces on OV and UV should be kept as small as
practical and the ENABLE_X and FAULT traces should
ideally not be routed under/over the OV/UV traces on
different PCB layers unless there is a ground or power plane
in between. Other methods that can be used to eliminate this
issue are by reducing the value of the resistors in the
network connected to UV and OV (R2, R3, R5 in Figure 16)
or by adding small decoupling capacitors to OV and UV (C2
and C7 in Figure 16). Both these methods act to reduce the
AC impedance at the nodes, although the latter method acts
to filter the signals which will also cause an increase in the
time that a UV/OV fault takes to be detected
.
When the ISL870XA is implemented on a hot swappable
card that is plugged into an always powered passive back
plane an RC filter is required on the V
IN
pin to prevent a high
dv/dt transient. With the already existing 1μF decoupling
capacitor the addition of a small series R (>50Ω) to provide a
time constant >50μs is all that is necessary.
FIGURE 15. LAYOUT DETAIL OF GND BETWEEN PINS 4 AND 5
PIN 4
PIN 5
GND
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
11
FN6381.0
October 12, 2006
.
FIGURE 16. ISL870XAEVAL1 PHOTOGRAPH AND SCHEMATIC OF LEFT CHANNEL
TIMING
COMPONENTS
RESISTORS
UV/OV SET
RESISTORS
PULL-UP
TABLE 1. ISL870XAEVAL1 LEFT CHANNEL COMPONENT LISTING
COMPONENT
DESIGNATOR COMPONENT FUNCTION COMPONENT DESCRIPTION
U1 ISL8702A, Quad Under/Overvoltage Sequencer Intersil, ISL8702A, Quad Under/Overvoltage Sequencer
R3 UV Resistor for Divider String 1.1kΩ 1%, 0603
R2 VMONITOR Resistor for Divider String 88.7kΩ 1%, 0603
R5 OV Resistor for Divider String 9.1kΩ 1%, 0603
C1 C
TIME
Sets Delay from Sequence Start to First ENABLE 0.01μF, 0603
R1 R
TD
Sets Delay from Third to Fourth ENABLE 120kΩ 1%, 0603
R9 R
TB
Sets Delay from First to Second ENABLE 3.01kΩ 1%, 0603
R7 R
TC
Sets Delay from Second to Third ENABLE 51kΩ 1%, 0603
R4, R6, R8, R10,
R11
ENABLE_X(#) and FAULT Pull-up Resistors 4kΩ 10%, 0402
C3 Decoupling Capacitor 1μF, 0603
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
12
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6381.0
October 12, 2006
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AM BS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45
o
C
H
0.25(0.010) BM M
α
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.3367 0.3444 8.55 8.75 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N14 147
α
0
o
8
o
0
o
8
o
-
Rev. 0 12/93
P1-P3P4-P6P7-P9P10-P12

ISL8703AIBZ-T

Mfr. #:
Buy ISL8703AIBZ-T
Manufacturer:
Renesas / Intersil
Description:
Supervisory Circuits ADJ QD SEQNCR 14N W/ANNEAL
Lifecycle:
New from this manufacturer.
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