MK3727DLFTR

DATASHEET
LOW COST 24 TO 36 MHZ 3.3 VOLT VCXO MK3727D
IDT™ / ICS™
LOW COST 24 TO 36 MHZ 3.3 VOLT VCXO 1
MK3727D REV M 030806
Description
The MK3727D combines the functions of a VCXO (Voltage
Controlled Crystal Oscillator) and PLL (Phase Locked
Loop) frequency doubler onto a single chip. Used in
conjunction with an external pullable quartz crystal, this
monolithic integrated circuit replaces more costly hybrid
(canned) VCXO devices. The MK3727D is designed
primarily for data and clock recovery applications within end
products such as ADSL modems, set-top box receivers,
and telecom systems.
The frequency of the on-chip VCXO is adjusted by an
external control voltage input into pin VIN. Because VIN is a
high impedance input, it can be driven directly from an
PWM RC integrator circuit. Frequency output increases
with VIN voltage input. The usable range of VIN is 0 to 3 V.
Features
24 to 36 MHz output frequency range (output frequency =
2x crystal frequency)
Uses an inexpensive 12 to 18 MHz external crystal
Ideal for ADSL applications using 17.664 MHz external
pullable crystal to generate locked 35.328 MHz clock
physical layer clock
Ideal for set-top box applications using 13.5 MHz external
pullable crystal to generate lock 27 MHz clock transport
video clock
On-chip VCXO with guaranteed pull range of ±115 ppm
minimum
VCXO input tuning voltage 0 to 3.3 V
Packaged in 8-pin SOIC (150 mil wide)
Available in Pb-free packaging
Block Diagram
24 to 36 MHz
(2x Crystal Frequency)
X1
X2
Voltage
Controlled
Crystal
Oscillator
PLL
Frequency
Doubler
VIN
12 to 18 MHz
Pullable
Crystal
MK3727D
LOW COST 24 TO 36 MHZ 3.3 VOLT VCXO VCXO AND SYNTHESIZER
IDT™ / ICS™
LOW COST 24 TO 36 MHZ 3.3 VOLT VCXO 2
MK3727D REV M 030806
Pin Assignment
Pin Descriptions
X1
VDD
VIN
GND
GND
NC
CLK
X21
2
3
4
8
7
6
5
8-Pin (150 mil)
SOIC
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 XI Input Crystal connection. Connect to the external pullable crystal.
2 VDD Power Connect to +3.3 V (0.01 µf decoupling capacitor recommended).
3 VIN Input Voltage input to VCXO – 0 to 3.3 V analog input which controls the
oscillation frequency of the VCXO.
4 GND Power Connect to ground.
5 CLK Output Clock output.
6 NC No internal connection (may connect to ground or VDD).
7 GND Power Connect to ground.
8 X2 Input Crystal connection. Connect to the external pullable crystal.
MK3727D
LOW COST 24 TO 36 MHZ 3.3 VOLT VCXO VCXO AND SYNTHESIZER
IDT™ / ICS™
LOW COST 24 TO 36 MHZ 3.3 VOLT VCXO 3
MK3727D REV M 030806
External Component Selection
The MK3727D requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND, as close to these pins as possible.
For optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output (CLK, pin 5)
and the load is over 1 inch, series termination should be
used. To series terminate a 50 trace (a commonly used
trace impedance), place a 33 resistor in series with the
clock line, as close to the clock output pin as possible. The
nominal impedance of the clock output is 20.
Quartz Crystal
The MK3727D VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To assure
the best system performance (frequency pull range) and
reliability, a crystal device with the recommended
parameters (shown below) must be used, and the layout
guidelines discussed in the following section shown must be
followed.
The frequency of oscillation of a quartz crystal is determined
by its “cut” and by the load capacitors connected to it. The
MK3727D incorporates on-chip variable load capacitors that
“pull” (change) the frequency of the crystal. The crystal
specified for use with the MK3727D is designed to have zero
frequency error when the total of on-chip + stray
capacitance is
14 pF.
Recommended Crystal Parameters:
Initial Accuracy at 25
°C ±20 ppm
Temperature Stability ±30 ppm
Aging ±20 ppm
Load Capacitance 14 pf
Shunt Capacitance, C0 7 pF Max
C0/C1 Ratio 250 Max
Equivalent Series Resistance 35 Max
The external crystal must be connected as close to the chip
as possible and should be on the same side of the PCB as
the MK3727D. There should be no vias between the crystal
pins and the X1 and X2 device pins. There should be no
signal traces underneath or close to the crystal.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture and
frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
The procedure for determining the value of these capacitors
can be found in application note MAN05.

MK3727DLFTR

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products LOW COST 24 TO 36MHZ 3.3V VCXO
Lifecycle:
New from this manufacturer.
Delivery:
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