AD768ARZ Datasheet AD768ARZ, AD768ARZ-REEL, AD768AR | P7-P9

REV. B

–6–

AD768

REFIN

– mA

POWER – mW

550

500

300

1.0 7.02.0 3.0 4.0 5.0 6.0

450

400

350

Figure 3. Power Dissipation vs. I

REFIN

Current

Note the AD768 is optimized for operation at an input current

of 5 mA. Both linearity and dynamic performance at other input

currents may be somewhat degraded. Figure 4 shows typical dc

linearity over a range of input currents. Figure 5 shows typical

SFDR (to Nyquist) performance over a range of input currents

and CLOCK input rates for a 1 MHz output frequency.

ERROR – LSB

REFIN

– mA

1.0 7.02.0 3.0 4.0 5.0 6.0

INL

DNL

Figure 4. INL/DNL vs. I

REFIN

Current

REFIN

– mA

SFDR – dB

–85

–55

1.0 7.02.0 3.0 4.0 5.0 6.0

–80

–75

–70

–65

–60

CLOCK = 10 MSPS

CLOCK = 20 MSPS

CLOCK = 30 MSPS

CLOCK = 40 MSPS

Figure 5. SFDR (to Nyquist) vs. I

REFIN

@ F

OUT

= 1 MHz

DAC TRANSFER FUNCTION

The AD768 may be used in either current-output mode with the

output connected to a virtual ground, or voltage-output mode

with the output connected to a resistive load.

In current output mode,

OUT

= (DAC CODE/65536) × (I

REFIN

× 4)

In voltage output mode,

OUT

= I

OUT

× R

LOAD

LAD

where:

DAC CODE is the decimal representation of the DAC inputs;

an integer between 0 and 65535.

REFIN

is the current applied at the IREFIN

pin, determined by

REF

Substituting for I

OUT

and

REFIN

OUT

= –V

REF

× (DAC CODE/65536) × 4 × [(R

LOAD

LAD

)/R

REF

]

These equations clarify an important aspect of the AD768

transfer function; the full-scale current output of the DAC is

proportional to a current input. The voltage output is then a

function of the ratio of (R

LOAD

LAD

)/R

REF

, allowing for cancel-

lation of resistor drift by selection of resistors with matched

characteristics.

REFERENCE INPUT

The IREFIN

pin is a current input node with low impedance to

REFCOM. This input current sets the magnitude of the DAC

current sources such that the full-scale output current is exactly

four times the current applied at IREFIN. For the nominal in-

put current of 5 mA, the nominal full-scale output current is

20 mA.

The 5 mA reference input current can be generated from the

on-chip 2.5 V reference with an external resistor of 500 Ω from

REFOUT to IREFIN. If desired, a variety of external reference

voltages may be used based on the selection of an appropriate

resistor. However, to maintain stability of the reference ampli-

fier, the external impedance at IREFIN must be kept below

1kΩ.

REFCOM

IREFIN

IFB

5mA

Figure 2. Equivalent Reference Input Circuit

The I

REFIN

current can be varied from 1 mA to 7 mA which

subsequently will result in a proportional change in the DAC

full-scale. Since the operating currents within the DAC vary

with I

REFIN

, so does the power dissipation. Figure 3 illustrates

that relationship.

AD768

REV. B

–7–

REFERENCE OUTPUT

The internal 2.5 V bandgap reference is provided for generation

of the I

REFIN

current, and must be compensated externally with

a capacitor of 0.1 µF or greater from REFOUT to REFCOM. If

an external reference is used, REFOUT should be tied directly

to the positive supply voltage, V

. This effectively turns off the

internal reference, eliminating the need for the external capaci-

tor at REFOUT. The reference is specified to drive a nominal

load of 5 mA with a maximum of 15 mA. Operation with a

heavier load will result in degradation of supply rejection and

reference voltage accuracy. Therefore, the reference output

should be buffered with an amplifier when additional load cur-

rent is required. A properly sized pull-up resistor can also be

used to source additional current to the load. The resistors value

should be selected such that REFOUT will always source a

minimum of 5 mA to IREFIN and the additional load.

AD768

IREFIN

REFOUT

REFCOM

REFCOMP

1µF

500Ω

Figure 6. Typical Reference Hookup

TEMPERATURE CONSIDERATIONS

Note that the reference plays a key role in the overall tempera-

ture performance of the AD768. Any drift of I

REFIN

shows up

directly in I

OUT.

When the output is taken as a current, the drift

of I

REFIN

(which depends on both V

REF

and R

REF

) must be mini-

mized. This can be done by using the internal temperature com-

pensated reference for V

REF

and a low temperature coefficient

resistor for R

REF.

If the output is taken as a voltage, it is a func-

tion of a resistor ratio, not an absolute resistor value.

By select-

ing resistors with matched temperature coefficients for R

REF

and R

LOAD,

the drift in the resistor values will cancel, providing

optimal drift performance.

REFERENCE NOISE REDUCTION AND MULTIPLYING

BANDWIDTH

For application flexibility and multiplying capabilities, the refer-

ence amplifier is designed to offer adjustable bandwidth that can

be reduced by connecting an external capacitor from the NR

node to the negative supply pin, V

. This capacitor limits the

bandwidth and acts as a filter to reduce the noise contribution

from the reference amplifier.

The noise reduction capacitor, C

, is not required for stability

and does not affect the settling time of the DAC output. With-

out this capacitor, the I

REFIN

bandwidth is 15 MHz allowing

high frequency modulation of the DAC full-scale range through

the reference input node. Figure 7 shows the relationship be-

tween the external noise reduction capacitor and the –3 dB

bandwidth of the reference amplifier.

NOISE REDUCTION CAPACITOR – F

BANDWIDTH – Hz

100M

10p 1µ100p 1n 10n 100n

10M

100k

10k

Figure 7. External Noise Reduction Capacitor vs. –3 dB

Bandwidth

The sensitivity of the NR node requires that care be taken in

capacitor placement. The capacitor should be located as physi-

cally close to the package pins as possible and lead lengths

should be minimized. For this purpose, the use of a chip

capacitor is recommended. For applications that do not require

high frequency modulation at IREFIN, it is recommended that

a capacitor on the order of 1 µF be connected from NR to V

If the reference input is purely dc, noise may be minimized with

multiple capacitors, such as 1 µF and 0.1 µF, to more effectively

filter both high and low frequency disturbances.

ANALOG OUTPUTS

The AD768 offers two analog outputs; IOUTA is trimmed for

optimal INL and DNL performance and has a full-scale output

when all bits are high. For applications that require the specified

dc accuracy, IOUTA should be used. IOUTB is the comple-

mentary output with full-scale output when all bits are low.

Both IOUTA and IOUTB provide similar dynamic perfor-

mance. Refer to Figures 8 and 9 for typical INL and DNL per-

formance curves. The outputs can also be used differentially.

Refer to the section “Applying the AD768” for examples of vari-

ous output configurations.

DIGITAL INPUT CODE – k

–8

06510 20 30 40

–2

–4

–6

INL ERROR – LSB

50 6051525354555

Figure 8. Typical INL Performance

REV. B

–8–

AD768

DIGITAL INPUT CODE – k

–8

06510 20 30 40

–2

–4

–6

DNL ERROR – LSB

50 6051525354555

Figure 9. Typical DNL Performance

The outputs have a compliance range of –1.2 V to +5.0 V with

respect to LADCOM. The current steering output stages will

remain functional over this range. Operation beyond the maxi-

mum compliance limits may cause either output stage saturation

or breakdown, resulting in nonlinear performance. The rated dc

and ac performance specifications are for an output voltage of

0 V to –1 V.

The current in LADCOM is proportional to I

REFIN

and has been

carefully configured to be independent of digital code when the

output is connected to a virtual ground. This minimizes any det-

rimental effects of ladder ground resistance on linearity. For

optimal dc linearity, IOUTA should be connected directly to a

virtual ground, and IOUTB should be grounded. An example of

this configuration is provided in the section “Buffered Voltage

Output.” If IOUTA is driving a resistive load directly, then

IOUTB should be terminated with an equal impedance. This

will ensure the current in LADCOM remains constant with digi-

tal code, and is recommended for improved dc linearity in the

unbuffered voltage output configuration.

As shown in Figure 10, there is an equivalent output impedance

of 1 kΩ in parallel with 3 pF at each output terminal. If the out-

put voltage deviates from the ladder common voltage, an error

current flows through this 1 kΩ impedance. This is a linear effect

which does not change with input code, so it appears as a gain

error. With 50 Ω output termination, the resulting gain error is

approximately –5%. An example of this configuration is pro-

vided in the section Unbuffered Voltage Output.

1kΩ 1kΩ

3pF 3pF

OUT

IREFIN

x2.75

LADCOM IOUTB

IOUTA

Figure 10. Equivalent Analog Output Circuit

DIGITAL INPUTS

The AD768 digital inputs consist of 16 data input pins and a

clock pin. The 16-bit parallel data inputs follow standard posi-

tive binary coding, where DB15 is the most significant bit

(MSB) and DB0 is the least significant bit (LSB). IOUTA pro-

duces full-scale output current when all data bits are at logic 1.

IOUTB is the complementary output, with full-scale when all

data bits are at logic 0. The full-scale current is split between

the two outputs as a function of the input code.

The digital interface is implemented using an edge-triggered

master slave latch. The DAC output is updated following the

rising edge of the clock, and is designed to support a clock rate

as high as 40 MSPS. The clock can be operated at any duty

cycle that meets the specified minimum latch pulse width. The

setup and hold times can also be varied within the clock cycle as

long as the specified minimums are met, although the location

of these transition edges may affect digital feedthrough. The

digital inputs are CMOS compatible with logic thresholds set to

approximately half the positive supply voltage. The small input

current requirements allow for easy interfacing to unbuffered

CMOS logic. Figure 11 shows the equivalent digital input

circuit.

DIGITAL

INPUT

DCOM

Figure 11. Equivalent Digital Input Circuit

Digital input signals to the DAC should be isolated from the

analog output as much as possible. Interconnect distances to the

DAC inputs should be kept as short as possible. Termination

resistors may improve performance if the digital lines become

too long. To minimize digital feedthrough, the inputs should be

free from glitches and ringing, and may be further improved

with a reduction of edge speed.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

AD768ARZ

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Digital to Analog Converters - DAC IC 16-BIT 30 MSPS

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AD768ARZ

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