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8T349316NLGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
DATASHEET
2.5V LVDS 1:16 Clock Fanout Buffer 8T349316
8T349316 REVISION 2 11/2/14 1 ©2014 Integrated Device Technology, Inc.
General Description
The 8T349316 is a 2.5V differential clock buffer with sixteen LVDS
outputs. The fanout from a differential input to the sixteen LVDS
outputs reduces loading on the preceding driver and provides an
efficient clock distribution network. The 8T349316 can act as a
translator from a differential HSTL, LVPECL, CML or LVDS input to
LVDS output signals. A single-ended 3.3V, 2.5V LVCMOS/LVTTL
input can also be used to translate to LVDS outputs. The redundant
input capability allows for an asynchronous change-over from a
primary clock source to a secondary clock source. Selectable
reference inputs are controlled by SEL. The 8T349316 outputs can
be asynchronously enabled/disabled. When disabled, the outputs
will drive to the value selected by the GL pin. Multiple power and
grounds reduce noise.The extended temperature range supports
wireless infrastructure, telecommunication and networking end
equipment requirements. The device is a member of the
high-performance clock family from IDT.
Features
• Clock signal selection and fanout to 16 LVDS outputs
• Guaranteed Low Skew < 50ps (max)
• Low output pulse skew < 125ps (max)
• Propagation delay < 1.75ns (max)
• Up to 1GHz clock signal operation
• Support the following input types: HSTL, LVPECL, HCSL, LVTTL
• Selectable differential input
• Power-down mode
• Full 2.5V power supply
• -40°C to +85°C ambient operating temperature
• Lead-free (RoHS 6) 52-lead VFQFN-P packaging
• Replacement device for the 5T9316
Block Diagram
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
POWER DOWN
CTRL
A1
nA1
A2
nA2
SEL
GL
nG1
nG2
nPD
1
0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
Q10
nQ10
Q11
nQ11
Q12
nQ12
Q13
nQ14
Q15
nQ15
Q16
nQ16
Pin Assignment
52
8T349316
GL
V
DD
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
V
DD
GND
nc
SEL
V
DD
Q16
nQ16
Q15
nQ15
Q14
nQ14
Q13
nQ13
V
DD
nPD
nc
nG2
V
DD
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
V
DD
A2
nA2
nG1
V
DD
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
V
DD
A1
nA1
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
51 50 49 48 47 46 45 44 43 42 41 40
14 15 16 17 17 19 20 21 22 23 24 25 26
52-lead VFQFN-P, EPad
8mm x 8mm x 0.9mm Package body
NL package
Top View
2.5V LVDS 1:16 CLOCK FANOUT BUFFER 2 REVISION 2 11/2/14
8T349316 DATASHEET
Pin Description and Pin Characteristic Tables
Table 1: Pin Descriptions
Number Name Type Description
1
nG1
Input -
Output enable control input for the Q[1:8] differential outputs.
See Table 3C. LVCMOS/LVTTL interface levels.
2
V
DD
Power Positive power supply voltage.
3
Q1
Output Differential clock output Q1. LVDS interface signals.
4
nQ1
Output Differential clock output Q1. LVDS interface signals.
5
Q2
Output Differential clock output Q2. LVDS interface signals.
6
nQ2
Output Differential clock output Q2. LVDS interface signals.
7
Q3
Output Differential clock output Q3. LVDS interface signals.
8
nQ3
Output Differential clock output Q3. LVDS interface signals.
9
Q4
Output Differential clock output Q4. LVDS interface signals.
10
nQ4
Output Differential clock output Q4. LVDS interface signals.
11
V
DD
Power Positive power supply voltage.
12
A1
Input - Differential clock signal input 1.
13
nA1
Input - Differential clock signal input 1.
14
GL
Input -
Control input for the output level for outputs in disable state.
See Table 3C and Table 3D. LVCMOS/LVTTL interface levels.
15
V
DD
Power Positive power supply voltage.
16
Q5
Output Differential clock output Q5. LVDS interface signals.
17
nQ5
Output Differential clock output Q5. LVDS interface signals.
18
Q6
Output Differential clock output Q6. LVDS interface signals.
19
nQ6
Output Differential clock output Q6. LVDS interface signals.
20
Q7
Output Differential clock output Q7. LVDS interface signals.
21
nQ7
Output Differential clock output Q7. LVDS interface signals.
22
Q8
Output Differential clock output Q8. LVDS interface signals.
23
nQ8
Output Differential clock output Q8. LVDS interface signals.
24
V
DD
Power Positive power supply voltage.
25
GND
Power Power Supply Ground.
26
nc
- - Not connected. It is recommended to connect this pin to board GND (0V).
27
nA2
Input - Differential clock signal input 2.
28
A2
Input - Differential clock signal input 2.
29
V
DD
Power Positive power supply voltage.
30
nQ9
Output Differential clock output Q9. LVDS interface signals.
31
Q9
Output Differential clock output Q9. LVDS interface signals.
32
nQ10
Output Differential clock output Q10. LVDS interface signals.
33
Q10
Output Differential clock output Q10. LVDS interface signals.
34
nQ11
Output Differential clock output Q11. LVDS interface signals.
REVISION 2 11/2/14 3 2.5V LVDS 1:16 CLOCK FANOUT BUFFER
8T349316 DATASHEET
35
Q11
Output Differential clock output Q11. LVDS interface signals.
36
nQ12
Output Differential clock output Q12. LVDS interface signals.
37
Q12
Output Differential clock output Q12. LVDS interface signals.
38
V
DD
Power Positive power supply voltage.
39
nG2
Input -
Output enable control input for the Q[9:16] differential outputs.
See Table 3D. LVCMOS/LVTTL interface levels.
40
nc
- - Not connected. It is recommended to connect this pin to board GND (0V).
41
nPD
Input -
Device power-down control input.
See Table 3B. LVCMOS/LVTTL interface levels.
42
V
DD
Power Positive power supply voltage.
43
nQ13
Output Differential clock output Q13. LVDS interface signals.
44
Q13
Output Differential clock output Q13. LVDS interface signals.
45
nQ14
Output Differential clock output Q14. LVDS interface signals.
46
Q14
Output Differential clock output Q14. LVDS interface signals.
47
nQ15
Output Differential clock output Q15. LVDS interface signals.
48
Q15
Output Differential clock output Q15. LVDS interface signals.
49
nQ16
Output Differential clock output Q16. LVDS interface signals.
50
Q16
Output Differential clock output Q16. LVDS interface signals.
51
V
DD
Power Positive power supply voltage.
52
SEL
Input
Reference input signal select control pin.
See Table 3A. LVCMOS/LVTTL interface levels.
—
GND
Power Exposed package ground supply voltage (GND). Connect to board GND.
Table 2. Pin Characteristics
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance GL, nG1, nG2, nPD, SEL 3 pF
Table 1: Pin Descriptions
Number Name Type Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

8T349316NLGI

Mfr. #:
Buy 8T349316NLGI
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 2.5V LVDS 1:16 Clock Fanout Buffer
Lifecycle:
New from this manufacturer.
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