MAX9951/MAX9952
Dual Per-Pin Parametric
Measurement Units
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Note 2: The device operates properly with different supply voltages with equally different voltage swings.
Note 3: Interpret errors expressed in terms of %FSR (percent of full-scale range) as a percentage of the end-point-to-end-point
range, i.e., for the ±64mA range, the full-scale range = 128mA, and a 1% error = 1.28mA.
Note 4: Case must be maintained ±5°C for linearity specifications.
Note 5: Tested in range C.
Note 6: Current linearity specifications are maintained to within 700mV of the clamp voltages when the clamps are enabled.
Note 7: Specified as the percent of full-scale range change at the output per volt change in the DUT voltage.
Note 8: V
CLLO_
and V
CLHI_
should differ by at least 700mV.
Note 9: The digital interface accepts +5V, +3.3V, and +2.5V CMOS logic levels. The voltage at V
L
adjusts the threshold.
Note 10: Guaranteed by design.
Note 11: Settling times are to 0.1% of FSR. C
X_
= 60pF.
Note 12: All settling times are specified using a single compensation capacitor (C
X_
) across all current-sense resistors. Use an indi-
vidual capacitor across each sense resistor for better performance across all current ranges, particularly the lower ranges.
Note 13: The propagation delay time is only guaranteed over the force-voltage output range. Propagation delay is measured by
holding V
SENSE_
steady and transitioning THMAX_ or THMIN_.
Note 14: Maximum serial clock frequency may diminish at V
L
< +3.3V.
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +12V, V
EE
= -7V, V
L
= +3.3V, C
CM_
= 120pF, C
L
= 100pF, T
A
= +25°C, unless otherwise noted. Specifications at T
A
= T
MIN
and T
A
= T
MAX
are guaranteed by design and characterization. Typical values are at T
A
= +25°C, unless otherwise noted.) (Note 2)
