6
FN9153.9
June 15, 2010
Shutdown Holdoff Time t
TSSHD
-245- ns
UGATE Rise Time t
RU
V
PVCC
= 12V, 3nF Load, 10% to 90% - 26 - ns
LGATE Rise Time t
RL
V
PVCC
= 12V, 3nF Load, 10% to 90% - 18 - ns
UGATE Fall Time t
FU
V
PVCC
= 12V, 3nF Load, 90% to 10% - 18 - ns
LGATE Fall Time t
FL
V
PVCC
= 12V, 3nF Load, 90% to 10% - 12 - ns
UGATE Turn-On Propagation Delay (Note 7) t
PDHU
V
PVCC
= 12V, 3nF Load, Adaptive - 10 - ns
LGATE Turn-On Propagation Delay (Note 7) t
PDHL
V
PVCC
= 12V, 3nF Load, Adaptive - 10 - ns
UGATE Turn-Off Propagation Delay (Note 7) t
PDLU
V
PVCC
= 12V, 3nF Load - 10 - ns
LGATE Turn-Off Propagation Delay (Note 7) t
PDLL
V
PVCC
= 12V, 3nF Load - 10 - ns
LG/UG Three-State Propagation Delay (Note 7) t
PDTS
V
PVCC
= 12V, 3nF Load - 10 - ns
OUTPUT (Note 7)
Upper Drive Source Current I
U_SOURCE
V
PVCC
= 12V, 3nF Load - 1.25 - A
Upper Drive Source Impedance R
U_SOURCE
150mA Source Current 1.25 2.0 3.0 Ω
Upper Drive Sink Current I
U_SINK
V
PVCC
= 12V, 3nF Load - 2 - A
Upper Drive Transition Sink Impedance R
U_SINK_TR
70ns with Respect to PWM Falling - 1.3 2.2 Ω
Upper Drive DC Sink Impedance R
U_SINK_DC
150mA Source Current 0.9 1.65 3.0 Ω
Lower Drive Source Current I
L_SOURCE
V
PVCC
= 12V, 3nF Load - 2 - A
Lower Drive Source Impedance R
L_SOURCE
150mA Source Current 0.85 1.25 2.2 Ω
Lower Drive Sink Current I
L_SINK
V
PVCC
= 12V, 3nF Load - 3 - A
Lower Drive Sink Impedance R
L_SINK
150mA Sink Current 0.60 0.80 1.35 Ω
OVER TEMPERATURE SHUTDOWN
Thermal Shutdown Setpoint -150- °C
Thermal Recovery Setpoint -108- °C
NOTES:
7. Limits should be considered typical and are not production tested.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNITS
Functional Pin Description
PACKAGE PIN #
PIN
SYMBOL FUNCTIONSOIC DFN
1 1 UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
2 2 BOOT Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 8 for guidance in choosing the capacitor value.
- 3, 8 N/C No Connection.
3 4 PWM The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation;
see “Three-State PWM Input” on page 7 for further details. Connect this pin to the PWM output of the controller.
4 5 GND Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
5 6 LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
6 7 VCC Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.
7 9 PVCC This pin supplies power to both upper and lower gate drives in ISL6613; only the lower gate drive in ISL6612. Its
operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin to GND.
8 10 PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
9 11 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
ISL6612, ISL6613
