© 2000 Fairchild Semiconductor Corporation DS010620 www.fairchildsemi.com
November 1989
Revised February 2000
DM74ALS125 Quad 3-STATE Buffer
DM74ALS125
Quad 3-STATE Buffer
General Description
This device contains four independent gates each of which
performs a non-inverting buffer function. The outputs have
the 3-STATE feature. The 3-STATE circuitry contains a fea-
ture that maintains the buffer outputs in 3-STATE (high
impedance state) during power supply ramp-up or ramp-
down. This eliminates bus glitching problems that arise
during power-up and power-down. To minimize the possi-
bility that two outputs will attempt to take a common bus to
opposite logic levels, the disable time is shorter than the
enable time of the outputs.
Features
■ Advanced low power oxide-isolated ion-implanted
Schottky TTL process
■ Functional and pin compatible with the 74LS counterpart
■ Switching response specified into 500Ω and 50 pF load
■ Switching response specifications guaranteed over full
temperature and V
CC
supply range
■ PNP input design reduces input loading
■ Low level drive current: 74ALS = 24 mA
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Functional Table
Y = A
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
Hi-Z = 3-STATE (Outputs are disabled)
Logic Diagram
Order Number Package Number Package Description
DM74ALS125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS125N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Input Output
AC Y
LL L
HL H
X H Hi-Z
